On the Complexity of Fixed-Size Bit-Vector Logics with Binary Encoded Bit-Width

13 pages•Published: August 19, 2013

Abstract

Bit-precise reasoning is important for many practical applications of
Satisfiability Modulo Theories (SMT). In recent years efficient approaches
for solving fixed-size bit-vector formulas have been developed. From
the theoretical point of view, only few results on the complexity of
fixed-size bit-vector logics have been published. In this paper we show
that some of these results only hold if unary encoding on the bit-width of
bit-vectors is used. We then consider fixed-size bit-vector logics with
binary encoded bit-width and establish new complexity results. Our proofs
show that binary encoding adds more expressiveness to bit-vector logics,
e.g. it makes fixed-size bit-vector logic even without uninterpreted
functions nor quantication NExpTime-complete. We also show that under
certain restrictions the increase of complexity when using binary encoding
can be avoided.

Keyphrases: bit precise reasoning, bit vector logics, complexity, decision procedure, nexptime, smt

In: Pascal Fontaine and Amit Goel (editors). SMT 2012. 10th International Workshop on Satisfiability Modulo Theories, vol 20, pages 44-56.

Links:	https://easychair.org/publications/paper/SF7
	https://doi.org/10.29007/cvnz