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The design and evaluation of hierarchical multi-level parallelisms for H.264 encoder on multi-core architecture

Wei Haitao (School of Computer Science & Technology, Huazhong University of Science & Technology, Wuhan, China)
Junqing Yu (School of Computer Science & Technology, Huazhong University of Science & Technology, Wuhan, China)
Jiang Li (School of Computer Science & Technology, Huazhong University of Science & Technology, Wuhan, China)

As a video coding standard, H.264 achieves high compress rate while keeping good fidelity. But it requires more intensive computation than before to get such high coding performance. A Hierarchical Multi-level Parallelisms (HMLP) framework for H.264 encoder is proposed which integrates four level parallelisms - frame-level, slice-level, macroblock-level and data-level into one implementation. Each level parallelism is designed in a hierarchical parallel framework and mapped onto the multi-cores and SIMD units on multi-core architecture. According to the analysis of coding performance on each level parallelism, we propose a method to combine different parallel levels to attain a good compromise between high speedup and low bit-rate. The experimental results show that for CIF format video, our method achieves the speedup of 33.57x-42.3x with 1.04x-1.08x bit-rate increasing on 8-core Intel Xeon processor with SIMD Technology.

Keywords: H.264 encoder, hierarchical multi-level parallelisms, multi-core architecture