A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation
IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Special Section on Solid-State Circuit Design - Architecture, Circuit, Device and Design Methodology
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation
Yohei NAKATA, Yuta KIMI, Shunsuke OKUMURA, Jinwook JUNG, Takuya SAWADA, Taku TOSHIKAWA, Makoto NAGATA, Hirofumi NAKANO, Makoto YABUUCHI, Hidehiro FUJIWARA, Koji NII, Hiroyuki KAWAI, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO
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Keywords: design for robustness, cache, variation tolerance, 7T/14T SRAM
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2014 Volume E97.C Issue 4 Pages 332-341

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Abstract
This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploits 7T/14T bit-enhancing SRAM and on-chip voltage/temperature monitoring circuit. 7T/14T bit-enhancing SRAM can reconfigure itself dynamically to a reliable bit-enhancing mode. The on-chip voltage/temperature monitoring circuit can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically change its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. Experimental result shows that it does not fail with 25% and 30% droop of Vdd and it provides 91 times better failure rate with a 35% droop of Vdd compared with the conventional design.
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© 2014 The Institute of Electronics, Information and Communication Engineers
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