一种异构片上网络路由算法的研究

计算机科学 ›› 2017, Vol. 44 ›› Issue (3): 70-72.doi: 10.11896/j.issn.1002-137X.2017.03.017

• 2015全国高性能计算学术年会 • 上一篇    下一篇

一种异构片上网络路由算法的研究

方娟,刘士建,刘思彤   

  1. 北京工业大学计算机学院 北京100124,北京工业大学计算机学院 北京100124,北京工业大学计算机学院 北京100124
  • 出版日期:2018-11-13 发布日期:2018-11-13
  • 基金资助:
    本文受国家自然科学基金(61202076,2)资助

Routing Algorithm Research on Heterogeneous Network on Chip

FANG Juan, LIU Shi-jian and LIU Si-tong   

  • Online:2018-11-13 Published:2018-11-13

摘要: 随着集成电路工艺的迅速发展,传统的片上网络由于缓存引起芯片面积开销和能耗增加,从而使得无缓存路由技术得到了广泛关注。通过消除缓存, 整体的流水线进程大大得到简化,性能得到提高。但当网络负载量较大时,数据包被多次偏转或误传,导致网络的延迟增加,系统健壮性较差。针对片上网络运行应用的多样性,异构网络作为一种相对灵活的网络结构,能有效地降低网络的传输时延,提高系统性能。文中设计了无缓存NoC和带缓存NoC两种路由方式相结合的异构片上网络,并匹配静态路由算法和动态的自适应路由算法(AFC)进行数据包的传输。同时,还提出了一种针对AFC的优化算法(AFC-LP),其通过对无缓存路由计算的二次仲裁,进一步降低了通信的平均时延,提高了网络性能。实验表明,AFC-LP算法相比于传统带缓存的维序X-Y路由算法,片上网络的平均延迟降低了28.4%,CPU每一时钟周期内所执行的指令数IPC(Instruction Per Cycle)提升了10.4%。

关键词: 异构片上网络,无缓存路由,路由算法

Abstract: With the fast development of integrated circuits,the traditional buffered NoC,due to the increase of chip area overhead and energy consumption from the buffer,have made the bufferless routing technology receive widespread attention.By eliminating the buffer,the whole process of the pipeline is greatly simplified,performance is improved.But when the network load is very large,the data packets are repeatedly deflected or misrouted,causing the increase of the whole network latency,and system robustness is poor.According to the diversity of network running’s applications,heterogeneous networks as a relatively flexible network structure can effectively reduce the transmission latency and improve the system performance.In this paper,a new type of heterogeneous NoC which is combined with the bufferless NoC and the buffered NoC was mainly designed,and it matches the static routing algorithm and adaptive routing algorithm (AFC) for packet transmission.At the same time,a kind of optimized algorithm AFC-LP based on AFC was proposed,through the second arbitration for bufferless routing to further reduce the average latency of communication and improve the network performance.The result of experiments shows that comparing to the traditional buffered order X-Y routing algorithm,the proposed AFC_LP algorithm reduces the average of network latency by 28.4%,and improves the instructions per cycle (IPC) by 10.4%.

Key words: Heterogeneous network on chip,Bufferless routing,Routing algorithms

[1] SHAO J C.a study on the performance optimization of network on chip with accelerated network [D].Hangzhou:Zhejiang University,2014.(in Chinese) 邵景成.带加速网络的片上网络性能优化研究[D].杭州:浙江大学,2014.
[2] MISHRA A K,VIJAYKRISHNAN N,DAS C R.A case for heterogeneous on-chip interconnects for CMPs[C]∥Proceeding of the 2011 38th Annual International Symposium on Computer Architecture.San Jose,CA:IEEE,2011:389-399.
[3] JAFRI SAR,HONG Y J,THOTTETHODI M,et al.Adaptive flow control for robust performance and energy[C]∥Proceeding of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.Atlanta,GA:IEEE,2010:433-444.
[4] FALLIN C,CARIK C,MUTLU O.CHIPPER:A low-complexity Bufferless Deflection Router[C]∥Proceeding of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture.San Antonio,TX:IEEE,2011:144-155.

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