Browser Not SupportedA Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip | IEEE Journals & Magazine | IEEE Xplore

Notice: IEEE Xplore is unable to display this page because you may be using an incompatible or unsupported browser.

For the best experience, please upgrade to a newer, supported browser using the links below. If you cannot upgrade your browser, a temporary IEEE Xplore site is available for basic searches with links to full-text.