Browser Not Supported23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power | IEEE Conference Publication | IEEE Xplore

Notice: IEEE Xplore is unable to display this page because you may be using an incompatible or unsupported browser.

For the best experience, please upgrade to a newer, supported browser using the links below. If you cannot upgrade your browser, a temporary IEEE Xplore site is available for basic searches with links to full-text.