Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST

Yoshiyuki NAKAMURA; Jacob SAVIR; Hideo FUJIWARA

doi:10.1093/ietisy/e88-d.6.1210

Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST

Yoshiyuki NAKAMURA, Jacob SAVIR, Hideo FUJIWARA

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Built-in self-test (BIST) hardware is included today in many chips. This hardware is used to test the chip's functional circuits. Since this BIST hardware is manufactured using the same technology as the functional circuits themselves, it is possible for it to be faulty. It is important, therefore, to assess the impact of this unreliable BIST on the product defect level after test. Williams and Brown's formula, relating the product defect level as a function of the manufacturing yield and fault coverage, is re-examined in this paper. In particular, special attention is given to the influence of an unreliable BIST on this relationship. We show that when the BIST hardware is used to screen the functional product, an unreliable BIST circuitry tends, in many cases, to reduce the effective fault coverage and increase the corresponding product defect level. The BIST unreliability impact is assessed for both early life phase, and product maturity phase.

Publication: IEICE TRANSACTIONS on Information Vol.E88-D No.6 pp.1210-1216

Publication Date: 2005/06/01

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DOI: 10.1093/ietisy/e88-d.6.1210

Type of Manuscript: PAPER

Category: Dependable Computing

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Yoshiyuki NAKAMURA, Jacob SAVIR, Hideo FUJIWARA, "Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST" in IEICE TRANSACTIONS on Information, vol. E88-D, no. 6, pp. 1210-1216, June 2005, doi: 10.1093/ietisy/e88-d.6.1210.
Abstract: Built-in self-test (BIST) hardware is included today in many chips. This hardware is used to test the chip's functional circuits. Since this BIST hardware is manufactured using the same technology as the functional circuits themselves, it is possible for it to be faulty. It is important, therefore, to assess the impact of this unreliable BIST on the product defect level after test. Williams and Brown's formula, relating the product defect level as a function of the manufacturing yield and fault coverage, is re-examined in this paper. In particular, special attention is given to the influence of an unreliable BIST on this relationship. We show that when the BIST hardware is used to screen the functional product, an unreliable BIST circuitry tends, in many cases, to reduce the effective fault coverage and increase the corresponding product defect level. The BIST unreliability impact is assessed for both early life phase, and product maturity phase.
URL: https://globals.ieice.org/en_transactions/information/10.1093/ietisy/e88-d.6.1210/_p

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@ARTICLE{e88-d_6_1210,
author={Yoshiyuki NAKAMURA, Jacob SAVIR, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST},
year={2005},
volume={E88-D},
number={6},
pages={1210-1216},
abstract={Built-in self-test (BIST) hardware is included today in many chips. This hardware is used to test the chip's functional circuits. Since this BIST hardware is manufactured using the same technology as the functional circuits themselves, it is possible for it to be faulty. It is important, therefore, to assess the impact of this unreliable BIST on the product defect level after test. Williams and Brown's formula, relating the product defect level as a function of the manufacturing yield and fault coverage, is re-examined in this paper. In particular, special attention is given to the influence of an unreliable BIST on this relationship. We show that when the BIST hardware is used to screen the functional product, an unreliable BIST circuitry tends, in many cases, to reduce the effective fault coverage and increase the corresponding product defect level. The BIST unreliability impact is assessed for both early life phase, and product maturity phase.},
keywords={},
doi={10.1093/ietisy/e88-d.6.1210},
ISSN={},
month={June},}

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TY - JOUR
TI - Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST
T2 - IEICE TRANSACTIONS on Information
SP - 1210
EP - 1216
AU - Yoshiyuki NAKAMURA
AU - Jacob SAVIR
AU - Hideo FUJIWARA
PY - 2005
DO - 10.1093/ietisy/e88-d.6.1210
JO - IEICE TRANSACTIONS on Information
SN -
VL - E88-D
IS - 6
JA - IEICE TRANSACTIONS on Information
Y1 - June 2005
AB - Built-in self-test (BIST) hardware is included today in many chips. This hardware is used to test the chip's functional circuits. Since this BIST hardware is manufactured using the same technology as the functional circuits themselves, it is possible for it to be faulty. It is important, therefore, to assess the impact of this unreliable BIST on the product defect level after test. Williams and Brown's formula, relating the product defect level as a function of the manufacturing yield and fault coverage, is re-examined in this paper. In particular, special attention is given to the influence of an unreliable BIST on this relationship. We show that when the BIST hardware is used to screen the functional product, an unreliable BIST circuitry tends, in many cases, to reduce the effective fault coverage and increase the corresponding product defect level. The BIST unreliability impact is assessed for both early life phase, and product maturity phase.
ER -