Area-Efficient Reconfigurable Architecture for Media Processing

Yukio MITSUYAMA; Kazuma TAKAHASHI; Rintaro IMAI; Masanori HASHIMOTO; Takao ONOYE; Isao SHIRAKAWA

doi:10.1093/ietfec/e91-a.12.3651

Special Section on VLSI Design and CAD Algorithms

Area-Efficient Reconfigurable Architecture for Media Processing

Yukio MITSUYAMA, Kazuma TAKAHASHI, Rintaro IMAI, Masanori HASHIMOTO, Takao ONOYE, Isao SHIRAKAWA

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Keywords: reconfigurable, media processing, multi-standard, area-efficiency, dynamic reconfiguration

JOURNAL RESTRICTED ACCESS

2008 Volume E91.A Issue 12 Pages 3651-3662

DOI https://doi.org/10.1093/ietfec/e91-a.12.3651

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Abstract

An area-efficient dynamically reconfigurable architecture is proposed, which is dedicated to media processing. To implement a compact but high performance device, which can be used in consumer applications, the reconfigurable architecture distinctively performs 8-bit operations required for media processing whereas fine-grained operations are executed with the cooperation of a host processor. A heterogeneous reconfigurable array is composed of four types of cells, for which configuration data size is reduced by focusing application domain on media processing. Implementation results show that a multi-standard video decoding can be achieved by the proposed reconfigurable architecture with 1.1×1.4mm² in a 90nm CMOS technology.

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