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Low Delay-Power Product Current-Mode Multiple Valued Logic for Delay-Insensitive Data Transfer Mechanism Myeong-Hoon OH Dong-Soo HAR Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E88-A No.5 pp.1379-1383 Publication Date: 2005/05/01 Online ISSN: DOI: 10.1093/ietfec/e88-a.5.1379 Print ISSN: 0916-8508 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: delay-insensitive data transfer, globally asynchronous locally synchronous system, current-mode multiple valued logic, Full Text: PDF(261.4KB)>>
Summary: Conventional delay-insensitive (DI) data encodings require 2N+1 wires for transferring N-bit. To reduce complexity and power dissipation of wires in designing a large scaled chip, a DI data transfer mechanism based on current-mode multiple valued logic (CMMVL), where N-bit data transfer can be performed with only N+1 wires, is proposed. The effectiveness of the proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings through simulation at the 0.25-µm CMOS technology. Simulation results with wire lengths of 4 mm or larger demonstrate that the CMMVL scheme significantly reduces delay-power product values of the dual-rail encoding with data rate of 5 MHz or more and the 1-of-4 encoding with data rate of 18 MHz or more. | ||||||||||
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