A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC)

Yuan-Long JEANG; Jer-Min JOU; Win-Hsien HUANG

doi:10.1093/ietfec/e88-a.12.3531

A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC)

Yuan-Long JEANG, Jer-Min JOU, Win-Hsien HUANG

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In this paper, a methodology based on a mix-mode interconnection architecture is proposed for constructing an application specific network on chip to minimize the total communication time. The proposed architecture uses a globally asynchronous communication network and a locally synchronous bus (or cross-bar or multistage interconnection network MIN). First, a local bus is given for a group of IP cores so that the communications within this local bus can be arranged to be exclusive in time. If the communications of some IP cores should be required to be completed within a given amount of time, then a non-blocking MIN or a crossbar switch should be made for those IP cores instead of a bus. Then, a communication ratio (CR) for each pair of local buses is provided by users, and based on the Huffman coding philosophy, a process is applied to construct a binary tree (BT) with switches on the internal nodes and buses on the leaves. Since the binary tree system is deadlock free (no cycle exists in any path), the router is just a relatively simple and cheap switch. Simulation results show that the proposed methodology and architecture of NOC is better on switching circuit cost and performance than the SPIN and the mesh architecture using our developed deadlock-free router.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.12 pp.3531-3538

Publication Date: 2005/12/01

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DOI: 10.1093/ietfec/e88-a.12.3531

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: VLSI Architecture

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Yuan-Long JEANG, Jer-Min JOU, Win-Hsien HUANG, "A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC)" in IEICE TRANSACTIONS on Fundamentals, vol. E88-A, no. 12, pp. 3531-3538, December 2005, doi: 10.1093/ietfec/e88-a.12.3531.
Abstract: In this paper, a methodology based on a mix-mode interconnection architecture is proposed for constructing an application specific network on chip to minimize the total communication time. The proposed architecture uses a globally asynchronous communication network and a locally synchronous bus (or cross-bar or multistage interconnection network MIN). First, a local bus is given for a group of IP cores so that the communications within this local bus can be arranged to be exclusive in time. If the communications of some IP cores should be required to be completed within a given amount of time, then a non-blocking MIN or a crossbar switch should be made for those IP cores instead of a bus. Then, a communication ratio (CR) for each pair of local buses is provided by users, and based on the Huffman coding philosophy, a process is applied to construct a binary tree (BT) with switches on the internal nodes and buses on the leaves. Since the binary tree system is deadlock free (no cycle exists in any path), the router is just a relatively simple and cheap switch. Simulation results show that the proposed methodology and architecture of NOC is better on switching circuit cost and performance than the SPIN and the mesh architecture using our developed deadlock-free router.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.12.3531/_p

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@ARTICLE{e88-a_12_3531,
author={Yuan-Long JEANG, Jer-Min JOU, Win-Hsien HUANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC)},
year={2005},
volume={E88-A},
number={12},
pages={3531-3538},
abstract={In this paper, a methodology based on a mix-mode interconnection architecture is proposed for constructing an application specific network on chip to minimize the total communication time. The proposed architecture uses a globally asynchronous communication network and a locally synchronous bus (or cross-bar or multistage interconnection network MIN). First, a local bus is given for a group of IP cores so that the communications within this local bus can be arranged to be exclusive in time. If the communications of some IP cores should be required to be completed within a given amount of time, then a non-blocking MIN or a crossbar switch should be made for those IP cores instead of a bus. Then, a communication ratio (CR) for each pair of local buses is provided by users, and based on the Huffman coding philosophy, a process is applied to construct a binary tree (BT) with switches on the internal nodes and buses on the leaves. Since the binary tree system is deadlock free (no cycle exists in any path), the router is just a relatively simple and cheap switch. Simulation results show that the proposed methodology and architecture of NOC is better on switching circuit cost and performance than the SPIN and the mesh architecture using our developed deadlock-free router.},
keywords={},
doi={10.1093/ietfec/e88-a.12.3531},
ISSN={},
month={December},}

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TY - JOUR
TI - A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC)
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3531
EP - 3538
AU - Yuan-Long JEANG
AU - Jer-Min JOU
AU - Win-Hsien HUANG
PY - 2005
DO - 10.1093/ietfec/e88-a.12.3531
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2005
AB - In this paper, a methodology based on a mix-mode interconnection architecture is proposed for constructing an application specific network on chip to minimize the total communication time. The proposed architecture uses a globally asynchronous communication network and a locally synchronous bus (or cross-bar or multistage interconnection network MIN). First, a local bus is given for a group of IP cores so that the communications within this local bus can be arranged to be exclusive in time. If the communications of some IP cores should be required to be completed within a given amount of time, then a non-blocking MIN or a crossbar switch should be made for those IP cores instead of a bus. Then, a communication ratio (CR) for each pair of local buses is provided by users, and based on the Huffman coding philosophy, a process is applied to construct a binary tree (BT) with switches on the internal nodes and buses on the leaves. Since the binary tree system is deadlock free (no cycle exists in any path), the router is just a relatively simple and cheap switch. Simulation results show that the proposed methodology and architecture of NOC is better on switching circuit cost and performance than the SPIN and the mesh architecture using our developed deadlock-free router.
ER -