A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter

Philipus Chandra OH; Akira MATSUZAWA; Win CHAIVIPAS

doi:10.1093/ietele/e90-c.6.1311

A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter

Philipus Chandra OH, Akira MATSUZAWA, Win CHAIVIPAS

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Conventional clock and data recovery (CDR) using a phase locked loop (PLL) suffers from problems such as long lock time, low frequency acquisition and harmonic locking. Consequently, a CDR system using a time to digital converter (TDC) is proposed. The CDR consists of simple arithmetic calculation and a TDC, allowing a fully digital realization. In addition, utilizing a TDC also allows the CDR to have a very wide frequency acquisition range. However, deterministic jitter is caused with each sample, because the system's sampling time period is changing slightly at each data edge. The proposed system does not minimize jitter, but it tolerates small jitter. Therefore, the system offers a faster lock time and a smaller sampling error. This proposed system has been verified on system level in a Verilog-A environment. The proposed method achieves faster locking within just a few data bits. The peak to peak jitter of the recovered clock is 60 ps and the RMS jitter of the recovered clock is 30 ps, assuming that the TDC resolution is 10 ps. In applications where a small jitter error can be tolerated, the proposed CDR offers the advantage of fast locking time and a small sampling error.

Publication: IEICE TRANSACTIONS on Electronics Vol.E90-C No.6 pp.1311-1314

Publication Date: 2007/06/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e90-c.6.1311

Type of Manuscript: Special Section LETTER (Special Section on Analog Circuits and Related SoC Integration Technologies)

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Philipus Chandra OH, Akira MATSUZAWA, Win CHAIVIPAS, "A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter" in IEICE TRANSACTIONS on Electronics, vol. E90-C, no. 6, pp. 1311-1314, June 2007, doi: 10.1093/ietele/e90-c.6.1311.
Abstract: Conventional clock and data recovery (CDR) using a phase locked loop (PLL) suffers from problems such as long lock time, low frequency acquisition and harmonic locking. Consequently, a CDR system using a time to digital converter (TDC) is proposed. The CDR consists of simple arithmetic calculation and a TDC, allowing a fully digital realization. In addition, utilizing a TDC also allows the CDR to have a very wide frequency acquisition range. However, deterministic jitter is caused with each sample, because the system's sampling time period is changing slightly at each data edge. The proposed system does not minimize jitter, but it tolerates small jitter. Therefore, the system offers a faster lock time and a smaller sampling error. This proposed system has been verified on system level in a Verilog-A environment. The proposed method achieves faster locking within just a few data bits. The peak to peak jitter of the recovered clock is 60 ps and the RMS jitter of the recovered clock is 30 ps, assuming that the TDC resolution is 10 ps. In applications where a small jitter error can be tolerated, the proposed CDR offers the advantage of fast locking time and a small sampling error.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.6.1311/_p

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@ARTICLE{e90-c_6_1311,
author={Philipus Chandra OH, Akira MATSUZAWA, Win CHAIVIPAS, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter},
year={2007},
volume={E90-C},
number={6},
pages={1311-1314},
abstract={Conventional clock and data recovery (CDR) using a phase locked loop (PLL) suffers from problems such as long lock time, low frequency acquisition and harmonic locking. Consequently, a CDR system using a time to digital converter (TDC) is proposed. The CDR consists of simple arithmetic calculation and a TDC, allowing a fully digital realization. In addition, utilizing a TDC also allows the CDR to have a very wide frequency acquisition range. However, deterministic jitter is caused with each sample, because the system's sampling time period is changing slightly at each data edge. The proposed system does not minimize jitter, but it tolerates small jitter. Therefore, the system offers a faster lock time and a smaller sampling error. This proposed system has been verified on system level in a Verilog-A environment. The proposed method achieves faster locking within just a few data bits. The peak to peak jitter of the recovered clock is 60 ps and the RMS jitter of the recovered clock is 30 ps, assuming that the TDC resolution is 10 ps. In applications where a small jitter error can be tolerated, the proposed CDR offers the advantage of fast locking time and a small sampling error.},
keywords={},
doi={10.1093/ietele/e90-c.6.1311},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter
T2 - IEICE TRANSACTIONS on Electronics
SP - 1311
EP - 1314
AU - Philipus Chandra OH
AU - Akira MATSUZAWA
AU - Win CHAIVIPAS
PY - 2007
DO - 10.1093/ietele/e90-c.6.1311
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2007
AB - Conventional clock and data recovery (CDR) using a phase locked loop (PLL) suffers from problems such as long lock time, low frequency acquisition and harmonic locking. Consequently, a CDR system using a time to digital converter (TDC) is proposed. The CDR consists of simple arithmetic calculation and a TDC, allowing a fully digital realization. In addition, utilizing a TDC also allows the CDR to have a very wide frequency acquisition range. However, deterministic jitter is caused with each sample, because the system's sampling time period is changing slightly at each data edge. The proposed system does not minimize jitter, but it tolerates small jitter. Therefore, the system offers a faster lock time and a smaller sampling error. This proposed system has been verified on system level in a Verilog-A environment. The proposed method achieves faster locking within just a few data bits. The peak to peak jitter of the recovered clock is 60 ps and the RMS jitter of the recovered clock is 30 ps, assuming that the TDC resolution is 10 ps. In applications where a small jitter error can be tolerated, the proposed CDR offers the advantage of fast locking time and a small sampling error.
ER -