Summary
|
For Full-Text PDF, please login, if you are a member of IEICE, or go to Pay Per View on menu list, if you are a nonmember of IEICE. |
|
Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation Riichiro TAKEMURA Kiyoo ITOH Tomonori SEKIGUCHI Satoru AKIYAMA Satoru HANZAWA Kazuhiko KAJIGAYA Takayuki KAWAHARA Publication IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.758-764 Publication Date: 2007/04/01 Online ISSN: 1745-1353 DOI: 10.1093/ietele/e90-c.4.758 Print ISSN: 0916-8516 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Memory Keyword: twin-cell DRAM array, write time, low voltage RAM, retention time, and plate-driven cell, Full Text: PDF(1.6MB)>>
Summary: A DRAM-cell array with 12-F2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation. The write and read-out times of the twin-cell array are shorter than those of a single-cell array by 70% and 40% respectively, because of parallel writing and reading of half charge to and from two memory cells. According to measured retention characteristics of the single cells, the twin-cell array improves retention time by 20% compared with the single-cell array at 1 V and keeps the retention time of the single-cell array at 0.4 V. Furthermore, the cell accepts the plate-driven scheme without the need of a dummy cell, lowering the necessary word-line voltage by 0.4 V. | |||||
|
