IEICE Trans - Multi-Ported Register File for Reducing the Impact of PVT Variation

Multi-Ported Register File for Reducing the Impact of PVT Variation

Yuuichirou IKEDA
Masaya SUMITA
Makoto NAGATA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E89-C    No.3    pp.356-363
Publication Date: 2006/03/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e89-c.3.356
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Signal Integrity and Variability
Keyword: 
multi-ported register file,  self timing circuits,  PVT variation,  crosstalk noise,  

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Summary: 
We have developed a 32-bit, 32-word, and 9-read, 7-write ported register file. This register file has several circuits and techniques for reducing the impact of process variation that is marked in recent process technologies, voltage variation, and temperature variation, so called PVT variation. We describe these circuits and techniques in detail, and confirm their effects by simulation and measurement of the test chip.