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A templated programmable architecture for highly constrained embedded HD video processing

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Abstract

The implementation of a video reconstruction pipeline is required to improve the quality of images delivered by highly constrained devices. These algorithms require high computing capacities—several dozens of GOPs for real-time HD 1080p video streams. Today’s embedded design constraints impose limitations both in terms of silicon budget and power consumption—usually 2 mm\(^2\) for half a Watt. This paper presents the eISP architecture that is able to reach 188 MOPs/mW with 94 GOPs/mm\(^2\) and 378 GOPs/mW using TSMC 65-nm integration technology. This fully programmable and modular architecture, is based on an analysis of video-processing algorithms. Synthesizable VHDL is generated taking into account different parameters, which simplify the architecture sizing and characterization.

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Notes

  1. An in-depth study of this point could help optimize the results obtained, but it is beyond the scope of this paper.

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Acknowledgements

Authors are grateful to Nicola Martin, Dominique Debize, John Rander and Jacques Bouchard for their valuable assistance in proofreading and improving accuracy in written skills in English.

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Authors and Affiliations

  1. CEA, LIST—CEA Saclay, Saclay, France

    Mathieu Thevenin, Renaud Schmit & Laurent Letellier

  2. University of Burgundy, Burgundy, France

    Michel Paindavoine & Barthelemy Heyrman

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Correspondence to Mathieu Thevenin.

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Thevenin, M., Paindavoine, M., Schmit, R. et al. A templated programmable architecture for highly constrained embedded HD video processing. J Real-Time Image Proc 16, 143–160 (2019). https://doi.org/10.1007/s11554-018-0808-6

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