Abstract
Off-the-shelf multicore systems are increasingly used in real-time fields, but hardware resource contention remains a key challenge. This work focuses on statically scheduled systems, common in real-time computing, and introduces a novel model for calculating worst-case contention delays. Under realistic assumptions, our model provides tight upper limits on these delays, considering the timing interference from other cores and their task sets. We present comprehensive evaluations demonstrating that our approach yields more accurate contention bounds compared to existing solutions. Additionally, we introduce an automated framework that simplifies the integration of our model into real-world scenarios, making it practical for industry professionals. This work not only tackles a critical issue in real-time multicore systems but also offers a precise, practical solution for managing inter-core timing interference.















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Deadline misses are to some extent deemed as acceptable in soft and firm real-time systems.
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Funding
This work has been partially funded by the EU Horizon program under grant agreements No.825184 and No.101092644, by the Spanish Government through projects PID2019-106774RB-C22 and PID2020-113172RB-I00, by the Government of Catalonia as Consolidated Research Group 2021-SGR-109 and by the Ministry of Economic Affairs and Digital Transformation, in conjunction with the European Union-NextGenerationEU (within the framework of the PRTR and the MRR), through the CLOUDLESS UNICO I+D CLOUD 2022.
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XP wrote the main manuscript text and prepared the figures. CM contributed in the tables creation and reviewed the manuscript, improving the overall quality of the paper.
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Palomo, X., Molina, C. ITER: an ITERative approach for inter-core timing analysis in statically scheduled cyclic executive systems on COTS multicore platforms for CRTES. J Supercomput 80, 19719–19770 (2024). https://doi.org/10.1007/s11227-024-06208-4
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DOI: https://doi.org/10.1007/s11227-024-06208-4