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Replacement techniques for dynamic NUCA cache designs on CMPs

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Abstract

The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have been proposed to address this problem. Furthermore, an efficient last-level cache is crucial in chip multiprocessors (CMP) architectures to reduce requests to the offchip memory, because of the significant speed gap between processor and memory. Therefore, a bank replacement policy that efficiently manages the NUCA cache is desirable. However, the decentralized nature of NUCA has eliminated the effectiveness of replacement policies because banks operate independently of each other, and hence their replacement decisions are restricted to a single NUCA bank. In this paper, we propose three different techniques to deal with replacements in NUCA caches.

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Notes

  1. The experimental methodology is described in Sect. 3.

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Authors and Affiliations

  1. Intel Barcelona Research Center, Intel Labs—UPC, Jordi Girona, 2908034, Barcelona, Spain

    Javier Lira & Antonio González

  2. Department of Computer Engineering and Mathematics, Universitat Rovira i Virgili, Avinguda dels Països Catalans, 2643007, Tarragona, Spain

    Carlos Molina

  3. Electrical Engineering Department, United States Naval Academy, 105 Maryland Avenue Annapolis, MD, 21402-5025, USA

    Ryan N. Rakvic

Authors
  1. Javier Lira
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  2. Carlos Molina
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  3. Ryan N. Rakvic
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  4. Antonio González
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Correspondence to Javier Lira.

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Lira, J., Molina, C., Rakvic, R.N. et al. Replacement techniques for dynamic NUCA cache designs on CMPs. J Supercomput 64, 548–579 (2013). https://doi.org/10.1007/s11227-012-0859-6

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