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Parallel hardware implementation of data hiding scheme for quality access control of grayscale image based on FPGA

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Abstract

Dither modulation is a well-known data hiding technique for the quality access control of the digital image. Sometimes, quality access control demands real-time hardware implementation to achieve low-power consumption, high-speed, and real time processing with greater reliability and at the same time, the scheme can be fitted with the existing consumer electronic devices. With this motivation, we proposed an efficient hardware architecture to implement a discrete cosine transform domain based quality access control scheme. The proposed very-large-scale-integration architecture is optimized by parallel processing and is implemented in a field programmable gate array. The architecture is tested over a large number of benchmark images. The scheme offers a 90% improvement in power consumption than the related implementations found in the literature. The scheme also achieves a very high throughput of 1.34 GB/s and 1.34 GB/s for the quality access control of encoder and decoder, respectively at a maximum operating frequency of 131.16 MHz, for the processing of (512 × 512) images.

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Acknowledgements

This study was supported by the Ministry of Science and Technology (MOST), Taiwan R.O.C., under Grant Number MOST 107-3113-E-155-001-CC2, 106-3113-E-155-001-CC2, 106-2221-E-155-036, 105-3113-E-155-001, 104-3113-E-155-001, 103-3113-E-155-001, 103-2221-E-155-028-MY3.

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Authors and Affiliations

  1. Department of Information Technology, MCKV Institute of Engineering, Liluah, Howrah, WB, India

    Amit Phadikar

  2. Department of Photonics Engineering, Yuan Ze University, Taoyuan, Taiwan

    Himadri Mandal & Tien-Lung Chiu

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  1. Amit Phadikar
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  2. Himadri Mandal
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  3. Tien-Lung Chiu
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Correspondence to Himadri Mandal or Tien-Lung Chiu.

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Phadikar, A., Mandal, H. & Chiu, TL. Parallel hardware implementation of data hiding scheme for quality access control of grayscale image based on FPGA. Multidim Syst Sign Process 31, 73–101 (2020). https://doi.org/10.1007/s11045-019-00650-x

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  • DOI: https://doi.org/10.1007/s11045-019-00650-x

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