FPGA implementation of robust and low complexity template-based watermarking for digital images | Multimedia Tools and Applications Skip to main content
Springer Nature Link
Log in

FPGA implementation of robust and low complexity template-based watermarking for digital images

  • Published:
Multimedia Tools and Applications Aims and scope Submit manuscript

Abstract

Watermarking is a widespread technique for information protection and an invisible alternative to quick response codes. The literature mainly considers software implementations of watermarking methods, even though there are applications for which hardware watermarking solutions become preferable or the only possible option due to increased speed, power, or information safety requirements. A convenient, flexible, and universal solution for hardware development is intellectual property (IP) cores. IP cores are building blocks for creating processors on FPGA or ASIC. The main objective of this work is to present the implementation of the robust watermarking method in the form of an IP core suitable for image processing systems on processors. The main contribution of this work is that it is the first hardware implementation of template-based watermarking for modern neural network-based extraction methods. The paper briefly discusses the existing hardware solutions for embedding data, describes the implemented watermarking method and the implementation itself, and provides the key indicators of the resulting solution and a link to the public repository with the solution. The proposed watermarking scheme has good imperceptibility (PSNR of 39.66), bpp of 0.00097, and BER of less than 3% for attacks. The implementation supports a frequency of 120 MHz.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
¥17,985 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price includes VAT (Japan)

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14

Similar content being viewed by others

Data availability

Data is available on GitHub DzhanashiaKrsitina/watermark_ip. Any additional data will be made available upon request.

References

  1. Hartung F, Kutter M (1999) Multimedia watermarking techniques. Proc IEEE 87:1079–1107. https://doi.org/10.1109/5.771066

    Article  Google Scholar 

  2. Roy A, Kokila J, Ramasubramanian N, Begum BS (2023) Device-specific security challenges and solution in IoT edge computing: a review. J Supercomput 79:20790–20825. https://doi.org/10.1007/s11227-023-05450-6

    Article  Google Scholar 

  3. Mohanty SP (2009) A secure digital camera architecture for integrated real-time digital rights management. J Syst Architect 55:468–480. https://doi.org/10.1016/j.sysarc.2009.09.005

    Article  Google Scholar 

  4. Ball J (2007) Designing soft-core processors for FPGAs. In: Nurmi J (ed) Processor design. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-5530-0_11

  5. Azzaz MS, Kaibou R, Smahi A (2023) FPGA implementation using novel co-design approach of real-time speech chaos based crypto-watermarking prototype. In: 2023 International Conference on Advances in Electronics, Control and Communication Systems (ICAECCS), IEEE, pp 1–6

  6. Karthigaikumar P, Baskaran K (2011) An ASIC implementation of a low power robust invisible watermarking processor. J Syst Architect 57:404–411. https://doi.org/10.1016/j.sysarc.2010.03.008

    Article  Google Scholar 

  7. Maity HK, Maity SP (2014) FPGA implementation of reversible watermarking in digital images using reversible contrast mapping. J Syst Softw 96:93–104. https://doi.org/10.1016/j.jss.2014.05.079

    Article  Google Scholar 

  8. Coltuc D, Chassery JM (2007) Very fast watermarking by reversible contrast mapping. IEEE Signal Process Lett 14:255–258. https://doi.org/10.1109/LSP.2006.884895

    Article  Google Scholar 

  9. Sabeeh LN, Al-Ibadi MA (2024) FPGA based accelerator for image steganography. In: Hassan F, Sunar N, Mohd Basri MA, Mahmud MSA, Ishak MHI, Mohamed Ali MS (eds) Methods and applications for modeling and simulation of complex systems. AsiaSim 2023. Communications in computer and information science, vol 1911. Springer, Singapore. https://doi.org/10.1007/978-981-99-7240-1_1

  10. Maity SP, Kundu MK (2013) Distortion free image-in-image communication with implementation in FPGA. AEU-Int J Electron C 67:438–447. https://doi.org/10.1016/j.aeue.2012.10.014

    Article  Google Scholar 

  11. Janakiraman S, Thenmozhi K, Rayappan JBB, Amirtharajan R (2019) Indicator-based lightweight steganography on 32-bit RISC architectures for IoT security. Multimed Tools Appl 78:31485–31513. https://doi.org/10.1007/s11042-019-07960-z

    Article  Google Scholar 

  12. Mahesh AA, Raja KB (2019) Design of an efficient steganography model using lifting based DWT and Modified-LSB Method on FPGA. Int J Adv Comput Sci Appl 10:226–231. https://doi.org/10.14569/ijacsa.2019.0101032

    Article  Google Scholar 

  13. Jing-yu S, Hong C, Gang W et al (2023) FPGA image encryption-steganography using a novel chaotic system with line equilibria. Digit Signal Process 134:103889. https://doi.org/10.1016/j.dsp.2022.103889

    Article  Google Scholar 

  14. Madhushree B, Basanth Kumar HB, Chennamma HR (2023) An exhaustive review of authentication, tamper detection with localization and recovery techniques for medical images. Multimed Tools Appl. https://doi.org/10.1007/s11042-023-16706-x

    Article  Google Scholar 

  15. Sivaraman R, Padmaa M, Sridevi A et al (2023) Pullikolam assisted medical image watermarking on reconfigurable hardware. Multimed Tools Appl 82:21193–21203. https://doi.org/10.1007/s11042-023-14725-2

    Article  Google Scholar 

  16. Swetha V, Evangeline Divya Sagayee G, Brintha JS et al (2023) Design of DCT hardware accelerator using FPGA for medical image authentication. In: 2023 International Conference on Bio Signals, Images, and Instrumentation (ICBSII), IEEE, pp. 1–5

  17. Bhattacharjee T, Maity HK, Maity SP (2022) On FPGA implementation in medical secret image sharing with data hiding. Multimed Tools Appl 81:18755–18781. https://doi.org/10.1007/s11042-022-12451-9

    Article  Google Scholar 

  18. Tahiri MA, Bencherqui A, Karmouni H et al (2023) Implementation of a steganography system based on hybrid square quaternion moment compression in IoMT. J King Saud Univ - Comput Inform Sci 35:101604. https://doi.org/10.1016/j.jksuci.2023.101604

    Article  Google Scholar 

  19. Shet KS, Aswath AR, Hanumantharaju MC, Gao XZ (2019) Novel high-speed reconfigurable FPGA architectures for EMD-based image steganography. Multimed Tools Appl 78:18309–18338. https://doi.org/10.1007/s11042-019-7187-2

    Article  Google Scholar 

  20. Zhang X, Wang S (2006) Efficient steganographic embedding by exploiting modification direction. IEEE Commun Lett 10:781–783. https://doi.org/10.1109/LCOMM.2006.060863

    Article  Google Scholar 

  21. Phadikar A, Mandal H, Chiu TL (2020) A novel QIM data hiding scheme and its hardware implementation using FPGA for quality access control of digital image. Multimed Tools Appl 79:12507–12532. https://doi.org/10.1007/s11042-019-08392-5

    Article  Google Scholar 

  22. Phadikar A, Mandal H, Chiu TL (2020) Parallel hardware implementation of data hiding scheme for quality access control of grayscale image based on FPGA. Multidimens Syst Signal Process 31:73–101. https://doi.org/10.1007/s11045-019-00650-x

    Article  Google Scholar 

  23. Ismail SM, Ghidan AM, Zaki PW (2020) Novel chaotic random memory indexing steganography on FPGA. AEU-Int J Electron C 125:153367. https://doi.org/10.1016/j.aeue.2020.153367

    Article  Google Scholar 

  24. Das S, Sunaniya AK, Maity R, Maity NP (2021) Efficient FPGA implementation and verification of difference expansion based reversible Watermarking with Improved time and resource utilization. Microprocess Microsyst 83:103732. https://doi.org/10.1016/j.micpro.2020.103732

    Article  Google Scholar 

  25. Tian J (2003) Reversible data embedding using a difference expansion. IEEE Trans Circuits Syst Video Technol 13:890–896. https://doi.org/10.1109/TCSVT.2003.815962

    Article  Google Scholar 

  26. Hussain S, Sheybani N, Neekhara P et al (2022) FastStamp: Accelerating neural steganography and digital watermarking of images on FPGAs. In: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD. Institute of Electrical and Electronics Engineers Inc

  27. Dzhanashia K, Evsutin O (2022) Low complexity template-based watermarking with neural networks and various embedding templates. Comput Electr Eng 102:108194. https://doi.org/10.1016/j.compeleceng.2022.108194

  28. Fang H, Chen D, Huang Q et al (2020) Deep template-based watermarking. IEEE Trans Circuits Syst Video Technol 8215:1–1. https://doi.org/10.1109/tcsvt.2020.3009349

    Article  Google Scholar 

  29. Yuan F, Zhan L, Pan P, Cheng E (2021) Low bit-rate compression of underwater image based on human visual system. Signal Process Image Commun 91:116082. https://doi.org/10.1016/j.image.2020.116082

    Article  Google Scholar 

Download references

Acknowledgements

This work is an output of a research project implemented as part of the Basic Research Program at the National Research University Higher School of Economics (HSE University). We are very grateful to the anonymous referees for their constructive comments and helpful suggestions to improve the quality of this paper.

Author information

Authors and Affiliations

  1. HSE University, 20 Myasnitskaya Ulitsa, Moscow, 101000, Russia

    Kristina Dzhanashia & Oleg Evsutin

Authors
  1. Kristina Dzhanashia
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Oleg Evsutin
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

Kritstina Dzhanashia:  Methodology, Writing – original draft, Writing – review & editing.

Oleg Evsutin:  Conceptualization, Methodology, Writing – original draft, Writing – review & editing, Funding acquisition.

Corresponding author

Correspondence to Oleg Evsutin.

Ethics declarations

Competing interests

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Dzhanashia, K., Evsutin, O. FPGA implementation of robust and low complexity template-based watermarking for digital images. Multimed Tools Appl 83, 58855–58874 (2024). https://doi.org/10.1007/s11042-023-17876-4

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11042-023-17876-4

Keywords

Search

Navigation