Indicator-based lightweight steganography on 32-bit RISC architectures for IoT security

Abstract

Embedded devices with highly constrained resources are emerging in numerous application areas which include wireless sensor networks, Radio-Frequency IDentification (RFID) tags, and Internet of Things (IoT). These devices need to typically communicate small payload in the form of text/image/audio for which security is exceptionally essential. Considering the resource limitation on constrained devices, many crypto algorithms and a few stego algorithms have been designed with lightweight properties. Majority of these algorithms have been tested for lightweight property only based on their algorithmic attributes. Conversely, ensuring such lightweight characteristics by analysing their feasibility to reside and run in a constrained environment based on the device’s architectural attribute is inevitable for IoT applications. This paper aims to contribute by proposing an indicator based lightweight Least Significant Bit (LSB) steganography algorithm and to compare it’s algorithmic and device dependent implementation aspects with similar algorithms on popular 32-bit Reduced Instruction Set Computer (RISC) microcontrollers used in IoT platforms. The proposed variable embedding algorithm achieves a Peak Signal to Noise Ratio (PSNR) of over 46 dB with Normalised Cross Correlation (NCC) & Structural Similarity Index Measure (SSIM) being 0.9999 and 0.9998 respectively for an average embedding capacity of 1.5 bits per pixel. In addition to the above mentioned benchmarking parameter results, the Regular & Singular (RS) group and Sample Pair (SP) steganalysis, were also carried out to validate the security level of the proposed algorithm. On analysing the suitability of the proposed algorithm in terms of timing performance and memory requirements by implementing on different IoT hardware, the microcontroller with PIC32 core achieves a higher embedding throughput of over 2.7 Mega bits per second with a smaller memory footprint of less than 2 KB. Finally, the results obtained from the proposed work outperform the microcontroller implementation of stego algorithms reported in the literature.

Appendix 1

1.1 Target devices

In this work, the following microcontrollers comprising most popular 32-bit CPU cores having high performance and low power consumption characteristics were chosen as target devices. The primary specifications of the selected target devices are compared in Table 12.

Table 12 Comparison between target devices used

1.2 ARM – LPC2148 Microcontroller

The LPC2148 microcontroller (https://www.nxp.com/docs/en/user-guide/UM10139.pdf) manufactured by the NXP Semiconductors has a 32 bit ARM7TDMI-S CPU which can operate at a maximum frequency of 60 MHz and follows Von-Neumann architecture. The ARM7TDMI-S can provide high performance and very low power consumption due to the implementation of RISC architecture and simplified decode mechanism for the instructions. This simplicity enables high instruction throughput and impressive real-time interrupt response.

The ARM7TDMI-S processor has two instruction sets, the standard 32-bit ARM instruction set, and 16-bit THUMB instruction set. It has 37 registers all of which are 32- bits long: 1 program counter, 1 Current Program Status Register (CPSR), 5 Saved Program Status Registers (SPSRs) and 30 General Purpose Registers (GPRs). The processor also has 7 operating modes. The User mode runs most of the task while other modes are meant for privileged operations such as interrupt/exception handling. The device provides 512 KB of on-chip program memory and 32 KB of on-chip SRAM. The ARM7TDMI-S CPU uses the ARM7 Local bus to interface on-chip memory controller, AMBA Advanced High-Performance Bus (AHB) for providing an interface to the interrupt controller and ARM Peripheral Bus (APB) for on-chip peripheral functions. It follows a 3 stage pipeline technique where, while one instruction is being executed, the second one is being decoded, and the third instruction is being fetched from memory. It has 2 power saving modes namely Idle and power down mode. It requires a supply voltage of 3.0 V to 3.6 V. The KEIL MDK Integrated Development Environment (IDE) comprising ARMCC compiler is widely used to develop application software for this embedded device.

1.3 PIC32MX150F128B Microcontroller

The PIC32MX150F128B microcontroller (http://ww1.microchip.com/downloads/en/DeviceDoc/60001168J.pdf) produced by Microchip has a CPU core PIC32 (MIPS32 M4K) with Harvard RISC architecture. The 50 MHz MIPS32 M4K processor core is divided into multifaceted, parallel working logic blocks that provide an efficient and high performance computing engine. The blocks include Execution Unit, autonomous Multiply/Divide Unit (MDU), System Control Coprocessor (CPO), Fixed Mapping Translation (FMT), Dual Internal Bus Interfaces, Power Management MIPS16e Support and Enhanced JTAG controller. The processor core execution unit implements load/store architecture with all the Arithmetic Logic Unit (ALU) operations like logical, shift, add and subtract being executed in a single cycle.

The core contains thirty-two 32-bit General Purpose Registers which are mainly used for integer operations and address calculations. The register file consists of two read and one write ports which can be bypassed to minimise the operation latency during the pipeline. Unlike the other processor core, the MIPS32 M4K follows a 5-stage pipeline. The CPU first fetches the instructions, decodes each of the instruction, then fetches source operands, executes each instruction and finally writes the result into the intended destinations. The Multiply/Divide unit also contains a separate pipeline for implementing the multiply and divide operations.

The device provides nine power-saving methods and modes that allow the user to balance power consumption with device performance. In all of the above techniques and modes, the power saving is being controlled by the software. The device provides 128 KB of on-chip program memory, 32 KB of on-chip RAM and 4GB of virtual memory address space. It requires a supply voltage of 1.8 V to 3.3 V. The opensource MPLAB IDE supports the device programming with PIC32-GCC compiler.

1.4 AVR – AT32UC3A0128 Microcontroller

The AT32UC3A0128 is a 32-bit microcontroller (http://ww1.microchip.com/downloads/en/DeviceDoc/doc32058.pdf) manufactured by Atmel and has AVR32 UC3 CPU which can be operated up to 66 MHz clock and follows Harvard RISC architecture. This system-on-chip microcontroller has a high performing and efficient core which is mainly designed for cost-sensitive embedded applications that emphasis more on low power consumption and high code density.

The register file is designed to hold sixteen 32-bit general purpose registers, a program counter, link register, and stack pointer. The processor core implements an AVR32A micro-architecture which is mainly used for smaller microcontrollers. The micro-architecture supports some instructions with multiple addressing modes to reduce the code size. Also, the frequently used instructions like add, which takes 2 operands, are extended to accept 3 operands. This format increases the performance by allowing addition and data moving in a single cycle. It provides a special set of instructions for performing DSP operations. The AVR32 UC has 3 memory interfaces: a High-speed Bus for instruction fetch, data access and slave interfacing. A local bus interface is also used for providing an interface between CPU and device specific high-speed systems like the fast GPIO ports and floating point units. The processor also contains a Memory Protection Unit and a fast and flexible interrupt controller for modern operating systems and real-time application. It also follows the 3 stage pipelining technique: fetch, decode and execute. The Power Manager controls the oscillators along with Phase Locked Loop (PLLs) and generates a clock when the device resets. The device provides 128 KB of on-chip program memory and 32 KB of on-chip RAM. It requires a supply voltage of 1.8 V to 3.3 V. The opensource Atmel Studio IDE with AVR- GCC compiler supports device programming.