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Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time

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Abstract

Capturing dynamic and hard to detect faults in static embedded memories is a significant challenge for DFT designers. Not only it demands at-speed testing, it also requires a large number of operations (generally greater than 24 consecutive reads per memcell) on each memory cell, which is hard to achieve at lower testing budgets. We present a comprehensive study done on resistive defects which lead to read recovery faults in 6T memcell SRAMs. A novel DFT technique has been proposed using calibrated variation in dummy path of self timed memories to capture hard to detect resistive faults in small number of operations. Results show 89% reduction in test time for a robust test on an industrial SRAM with 2048 words operating at 400 MHz.

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References

  1. Adams RD, Cooley ES (1997) False write through and un-restored write electrical level fault models for SRAMs. Memory technology, design and testing, 1997. Proceedings., International Workshop on, pp 27–32, 11–12 Aug

  2. Al-Ars Z, van de Goor AJ (2001) Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs. Design, automation and test in Europe, 2001. Conference and exhibition 2001. Proceedings, pp 496–503

  3. Baker K et al (1999) Defect-based delay testing of resistive vias-contacts. A critical evaluation. Proc Int’l Test Conf (ITC), pp 467–476

  4. Dilillo L, Al-Hashimi BM (2007) March CRF: an efficient test for complex read faults in SRAM memories. Design and diagnostics of electronic circuits and systems, 2007. DDECS ′07. IEEE, pp 1–6, 11–13 April

  5. Dilillo L, Girard P, Pravossoudovitch S, Virazel A, Bastian M (2005) Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 μm and 90 nm technologies. Design automation conference, 2005. Proceedings. 42nd, pp 857–862, 13–17 June

  6. García J, Corbal J, Cerdá L, Valero M. Design and implementation of high-performance memory systems for future packet buffers. Proceedings of the 36th International Symposium on Microarchitecture (MICRO–36′03)

  7. Gerosa G, Alexander M, Alvarez J, Croxton C, D’Addeo M, Kennedy AR, Nicoletta C, Nissen JP, Philip R, Reed P, Sanchez H, Taylor SA, Burgess B (1997) A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller. Solid-State Circuits, IEEE Journal of 32(11): 1635–1649, Nov

    Google Scholar 

  8. Hamdioui S, Wadsworth R, Delos Reyes J, van de Goor AJ (2003) Importance of dynamic faults for new SRAM technologies. European Test Workshop, 2003. Proceedings. The Eighth IEEE, pp 29–34, 25–28 May

  9. Khare JB, Shah AB, Raman A, Rayas G (2006) Embedded memory field returns–trials and tribulations. Test conference, 2006. ITC ′06. IEEE International, pp 1–6, 22–27 Oct

  10. Li JCM, Tseng C-W; McCluskey EJ (2001) Testing for resistive opens and stuck opens. Test conference, 2001. Proceedings. International, pp 1049–1058

  11. Montanes RR, de Gyvez JP, Volf P (2002) Resistance characterization for weak open defects. Design & Test of Computers, IEEE 19(5):18–26

    Article  Google Scholar 

  12. Needham W, Prunty C, Eng Hong Yeoh (1998) High volume microprocessor test escapes, an analysis of defects our tests are missing. Test conference, 1998. Proceedings. International, pp 25–34, 18–23 Oct

  13. Sachdev M (1996) Test and testability techniques for open defects in RAM address decoders. European design and test conference, 1996. ED&TC 96. Proceedings, pp 428–434, 11–14 Mar

  14. Sachdev M (1997) Open defects in CMOS RAM address decoders. Design & Test of Computers, IEEE 14(2):26–33

    Article  MathSciNet  Google Scholar 

  15. Segura J, Hawkins C. How it works, how it fails. CMOS Electronics, pp 0, Wiley-IEEE Press

  16. Sharifkhani M, Jahinuzzaman SM, Sachdev M (2006) Dynamic data stability in SRAM cells and its implications on data stability tests. Memory technology, design, and testing, 2006. MTDT ′06. 2006 IEEE International Workshop on, pp 7, pp 2–4 Aug

  17. van de Goor Ad J, Al-Ars Z (2000) Functional memory faults: a formal notation and a taxonomy. VLSI test symposium, 2000. Proceedings. 18th IEEE, pp 281–289

  18. Virazel A et al (2005) Analysis of dynamic faults in embedded-SRAMs: implications for memory test. Journal of electronic testing: Theory and Applications 21:169–179

    Article  Google Scholar 

  19. Yamauchi H (2009) Prospects for variation tolerant SRAM circuit designs. ASIC, 2009. ASICON ′09. IEEE 8th International Conference on, pp 621–624, 20–23 Oct

  20. Zarrineh K, Deo AP, Adams RD (2000) Defect analysis and realistic fault model extensions for static random access memories. Memory technology, design and testing, 2000. Records of the 2000 IEEE International Workshop on, pp 119–124

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Authors and Affiliations

  1. ST Microelectronics India Pvt Ltd., Plot No.1, Knowledge Park III, Greater Noida, India

    Prashant Dubey & Akhil Garg

  2. University of Michigan, Ann Arbor, MI, 48109, USA

    Shashank Mahajan

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  1. Prashant Dubey
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  2. Akhil Garg
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  3. Shashank Mahajan
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Correspondence to Prashant Dubey.

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Responsible Editor: M. Sachdev

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Dubey, P., Garg, A. & Mahajan, S. Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time. J Electron Test 26, 659–666 (2010). https://doi.org/10.1007/s10836-010-5176-5

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  • DOI: https://doi.org/10.1007/s10836-010-5176-5

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