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Majority Logic Mapping for Soft Error Dependability

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Abstract

This work proposes the use of analog majority gates to implement combinational circuits that are intrinsically tolerant to transient faults. A new type of voter circuit, that uses some knowledge from the analog design arena is proposed, together with a new mapping approach to implement circuits given their input/output table. This new mapping approach is shown to compare favorably against a classic mapping. The implementation and validation of an adder circuit, using conventional triple modular redundancy (TMR), the classic mapping, and the proposed solution are analyzed, in order to confirm that the shown technique is indeed fault tolerant, and has advantages in terms of area and performance when compared to TMR. Finally, implementations of a subset of the ISCAS 85 benchmark circuits using TMR with the analog voter and the proposed approach are compared and the results analyzed.

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Acknowledgment

The authors would like to thank Álisson Michels, Cristiano Lazzari, and Simone Bavaresco for their help in the learning process of different tools.

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Authors and Affiliations

  1. Departamento de Informática Aplicada, Instituto de Informática, PPGC, Universidade Federal do Rio Grande do Sul, Av. Bento Gonçalves 9500, Bloco 4, Prédio 43412, 91501-970, Porto Alegre, Rio Grande do Sul, Brazil

    Lorenzo Petroli, Carlos Arthur Lang Lisboa, Fernanda Lima Kastensmidt & Luigi Carro

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  1. Lorenzo Petroli
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  2. Carlos Arthur Lang Lisboa
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  3. Fernanda Lima Kastensmidt
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  4. Luigi Carro
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Corresponding author

Correspondence to Carlos Arthur Lang Lisboa.

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Responsible Editor: N. A. Touba

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Petroli, L., Lisboa, C.A.L., Kastensmidt, F.L. et al. Majority Logic Mapping for Soft Error Dependability. J Electron Test 24, 83–92 (2008). https://doi.org/10.1007/s10836-007-5044-0

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  • DOI: https://doi.org/10.1007/s10836-007-5044-0

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