Investigation into the Use of Hybrid Solutions for ΣΔ A/D Converter Testing

Abstract

ΣΔ ADCs are now extensively used in electronic system applications requiring high resolution analogue to digital interfaces. Many of these applications require low cost solutions that imply the need for efficient production test strategies for verifying performance specifications. Industrial state-of-the-art is based on DSP testing to extract dynamic performance such as THD and SNR from an FFT on a sampled bit-stream from the decimator output. This method is computationally expensive and as resolution increases, the total number of samples required also increases thus pushing total test time beyond acceptable limits. This paper proposes an alternative hybrid solution based on an initial low-cost wafer level screening test followed by a DSP based technique on marginal devices based on alternative DSP transforms. The screening test is applied to the high-frequency bit-stream output of the ΣΔ modulator and has potential for on-chip implementation. Relatively simple algorithms and cross-correlation techniques are used that can associate specific changes in the bit-stream pattern to key failure modes affecting dynamic performance parameters. A simplified supplementary DSP test for marginal devices is proposed that is less computationally intensive than FFT analysis.