Abstract
Current paper presents a unified approach for calculating mixed-level testability measures. In addition, a new method of testability guided RTL Automated Test Pattern Generation (ATPG) for sequential circuits is introduced. The methods and algorithms are based on path tracing procedures on decision diagrams. The previous known methods have been implemented in test synthesis and in guiding gate-level test generation. However, works on application of testability measures to guide high-level test generation are missing. The main aim of this paper is to bridge this gap. Current method is compared to a recent approach known from the test synthesis area. Experiments show that testability measures greatly influence the fault coverage in RT-level test generation with the proposed approach achieving the best results. Similar to earlier works, our research confirms that RT-level fault coverage is in correlation with logic level one.
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Raik, J., Nõmmeots, T. & Ubar, R. A New Testability Calculation Method to Guide RTL Test Generation. J Electron Test 21, 71–82 (2005). https://doi.org/10.1007/s10836-005-5288-5
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DOI: https://doi.org/10.1007/s10836-005-5288-5