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Design and Evaluation of a Carbon Nanotube-Based Programmable Architecture

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Abstract

In the hunt to find a replacement to CMOS, material scientists are developing a wide range of nanomaterials and nanomaterial-based devices that offer significant performance improvements. One example is the Carbon Nanotube Field Effect Transistor, or CNFET, which replaces the traditional silicon channel with an array of semiconducting carbon nanotubes (CNTs). Given the increased variation and defects of nanometer-scale fabrication, and the regular nature of bottom-up self-assembly, field programmable devices are a promising initial application for such technologies. In this paper, we detail the design and evaluation of a novel nanomaterial-based architecture called FPCNA (Field Programmable Carbon Nanotube Array). New nanomaterial-based circuit building blocks are developed and characterized, including a lookup table created entirely from continuous CNT ribbons. To accurately determine the performance of these building blocks, we create variation-aware physical design tools with statistical timing analysis that can handle both Gaussian and non-Gaussian random variables. When the FPCNA architecture is evaluated using this CAD flow, we see a 2.75× performance improvement over an equivalent CMOS FPGA at a 95% yield. In addition, FPCNA offers a 5.07× footprint reduction compared to the baseline FPGA.

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  1. Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL, USA

    Scott Chilstedt, Chen Dong & Deming Chen

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  1. Scott Chilstedt
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  2. Chen Dong
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Correspondence to Scott Chilstedt.

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Chilstedt, S., Dong, C. & Chen, D. Design and Evaluation of a Carbon Nanotube-Based Programmable Architecture. Int J Parallel Prog 37, 389–416 (2009). https://doi.org/10.1007/s10766-009-0105-x

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