Abstract
Synthesizing finite-state systems from full linear-time temporal logic (LTL) is an ambitious way to tackle the challenge of constructing correct-by-construction systems. One particularly promising approach in this context is bounded synthesis, originally proposed by Schewe and Finkbeiner, which in turn builds upon Safraless synthesis, as described by Kupferman and Vardi. Previous implementations of these approaches performed the computation either in an explicit way or used symbolic data structures other than binary decision diagrams (BDDs). In this paper, we reconsider BDDs as state space representation and use it as data structure for bounded synthesis. The key to this construction is the application of two novel optimisation techniques that decrease the number of state bits in such a representation significantly. The first technique uses signalling bits to connect sub-games representing the safety- and non-safety parts of the specification. The second technique is based on a closer analysis of the step of building a safety game from a universal automaton and uses a sufficient condition to remove some so-called counters from the state space of the game.
We evaluate our approach on several benchmark suites and show that the new approach leads to a computation time improvement of several orders of magnitude.
Similar content being viewed by others
Notes
While this representation of the winning condition is rather uncommon in the literature, it will allow us later to discuss the composition of games in a simplified way.
In other words, whether a play is winning for player 1 can be determined by evaluating which of the sets of \(\mathcal{S}(\mathcal{F})\) contain a position that is visited along the play, and then substituting all sets in \(\mathcal{F}\) for which some position is visited along the play by true and the other ones by false. If the resulting Boolean formula evaluates to true, the play is winning for player 1. While this definition of the acceptance condition is uncommon for obligation games in the literature, we use it here as it is very helpful to describe the game compositions in the following chapters in a simple and intuitive way.
The solution process described here is related to solving so-called games with a weak winning condition (see [13] for a definition and details) and a reformulation of a procedure for solving games with a weak transition structure (with uniform treatment of all game positions in a strongly connected component, see [19] for a definition and details).
A similar idea was also pursued by Henzinger et al. [20] for simplifying the process of automaton determinisation.
References
Alur R, Madhusudan P, Nam W (2005) Symbolic computational techniques for solving games. Int J Softw Tools Technol Transf 7(2):118–128
Andersen HR (1994) Model checking and Boolean graphs. Theor Comput Sci 126(1):3–30
Bloem R, Cimatti A, Pill I, Roveri M (2007) Symbolic implementation of alternating automata. Int J Found Comput Sci 18(4):727–743
Bloem R, Galler S, Jobstmann B, Piterman N, Pnueli A, Weiglhofer M (2007) Specify, compile, run: hardware from PSL. Electron Notes Theor Comput Sci 190(4):3–16
Bloem R, Galler SJ, Jobstmann B, Piterman N, Pnueli A, Weiglhofer M (2007) Interactive presentation: automatic hardware synthesis from specifications: a case study. In: Lauwereins R, Madsen J (eds) DATE. ACM Press, New York, pp 1188–1193
Bloem R, Chatterjee K, Greimel K, Henzinger TA, Jobstmann B (2010) Robustness in the presence of liveness. In: Touili T, Cook B, Jackson P (eds) Computer aided verification. Lecture notes in computer science, vol 6174. Springer, Berlin, pp 410–424
Bozga M, Maler O, Pnueli A, Yovine S (1997) Some progress in the symbolic verification of timed automata. In: Grumberg O (ed) Computer aided verification. Lecture notes in computer science, vol 1254. Springer, Berlin, pp 179–190
Bryant RE (1986) Graph-based algorithms for Boolean function manipulation. IEEE Trans Comput 35(8):677–691
Burch JR, Clarke EM, McMillan KL, Dill DL, Hwang LJ (1992) Symbolic model checking: 1020 states and beyond. Inf Comput 98(2):142–170
Cimatti A, Clarke EM, Giunchiglia E, Giunchiglia F, Pistore M, Roveri M, Sebastiani R, Tacchella A (2002) NuSMV 2: an opensource tool for symbolic model checking. In: Brinksma E, Larsen KG (eds) Computer aided verification. Lecture notes in computer science, vol 2404. Springer, Berlin, pp 359–364
Cleaveland R, Steffen B (1991) A linear-time model-checking algorithm for the alternation-free modal μ-calculus. In: Larsen KG, Skou A (eds) Computer aided verification. Lecture notes in computer science, vol 575. Springer, Berlin, pp 48–58
Drechsler R, Sieling D (2001) Binary decision diagrams in theory and practice. Int J Softw Tools Technol Transf 3(2):112–136
Farwer B (2001) ω-automata. In: Grädel E, Thomas W, Wilke T (eds) Automata, logics, and infinite games. Lecture notes in computer science, vol 2500. Springer, Berlin, pp 3–20
Filiot E, Jin N, Raskin JF (2009) An antichain algorithm for LTL realizability. In: Computer aided verification. Lecture notes in computer science, vol 5643. Springer, Berlin, pp 263–277
Filiot E, Jin N, Raskin JF (2010) Compositional algorithms for LTL synthesis. In: Bouajjani A, Chin WN (eds) ATVA. Lecture notes in computer science, vol 6252. Springer, Berlin, pp 112–127
Finkbeiner B, Schewe S (2007) SMT-based synthesis of distributed systems. In: Automated formal methods (AFM)
Gastin P, Oddoux D (2001) Fast LTL to Büchi automata translation. In: Computer aided verification. Lecture notes in computer science, vol 2102. Springer, Berlin, pp 53–65
Godhal Y, Chatterjee K, Henzinger T (2011) Synthesis of AMBA AHB from formal specification: a case study. Int J Softw Tools Technol Transf. doi:10.1007/s10009-011-0207-9
Helmert M, Mattmüller R, Schewe S (2006) Selective approaches for solving weak games. In: Graf S, Zhang W (eds) ATVA. Lecture notes in computer science, vol 4218. Springer, Berlin, pp 200–214
Henzinger TA, Piterman N (2006) Solving games without determinization. In: Ésik Z (ed) CSL. Lecture notes in computer science, vol 4207. Springer, Berlin, pp 395–410
Jobstmann B, Bloem R (2006) Optimizations for LTL synthesis. In: FMCAD. IEEE Computer Society Press, Los Alamitos, pp 117–124
Klein U, Pnueli A (2010) Revisiting synthesis of GR(1) specifications. In: HVC. Lecture notes in computer science, vol 6504. Springer, Berlin
Kukula JH, Shiple TR (2000) Building circuits from relations. In: Emerson EA, Sistla AP (eds) Computer aided verification. Lecture notes in computer science, vol 1855. Springer, Berlin, pp 113–123
Kupferman O, Vardi MY (1999) Model checking of safety properties. In: Halbwachs N, Peled D (eds) Computer aided verification. Lecture notes in computer science, vol 1633. Springer, Berlin, pp 172–183
Kupferman O, Vardi MY (2005) Safraless decision procedures. In: FOCS. IEEE Press, New York, pp 531–542
Kupferman O, Lustig Y, Vardi M (2006) On locally checkable properties. In: Logic for programming, artificial intelligence, and reasoning, pp 302–316. doi:10.1007/11916277_21
McMillan KL (1993) Symbolic model checking. Kluwer Academic, Dordrecht
Piterman N (2007) From nondeterministic Büchi and Streett automata to deterministic parity automata. Log Methods Comput Sci 3(3)
Piterman N, Pnueli A, Sa’ar Y (2006) Synthesis of reactive(1) designs. In: Emerson EA, Namjoshi KS (eds) VMCAI. Lecture notes in computer science, vol 3855. Springer, Berlin, pp 364–380
Pnueli A (1977) The temporal logic of programs. In: FOCS. IEEE Press, New York, pp 46–57
Pnueli A, Rosner R (1989) On the synthesis of an asynchronous reactive module. In: Ausiello G, Dezani-Ciancaglini M, Rocca SRD (eds) ICALP. Lecture notes in computer science, vol 372. Springer, Berlin, pp 652–671
Schewe S, Finkbeiner B (2007) Bounded synthesis. In: Namjoshi KS, Yoneda T, Higashino T, Okamura Y (eds) ATVA. Lecture notes in computer science, vol 4762. Springer, Berlin, pp 474–488
Schneider K, Logothetis G (1999) Abstraction of systems with counters for symbolic model checking. In: Mutz M, Lange N (eds) Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen. Shaker, Braunschweig, pp 31–40
Sistla AP (1985) On characterization of safety and liveness properties in temporal logic. In: PODC, pp 39–48
Sohail S, Somenzi F (2009) Safety first: A two-stage algorithm for LTL games. In: FMCAD. IEEE Computer Society Press, Los Alamitos, pp 77–84
Somenzi F (2009) CUDD: CU decision diagram package, release 2.4.2
Thomas W (2002) Infinite games and verification (extended abstract of a tutorial). In: Brinksma E, Larsen KG (eds) Computer aided verification. Lecture notes in computer science, vol 2404. Springer, Berlin, pp 58–64
Thomas W (2008) Solution of Church’s problem: a tutorial. In: Apt K, Rooij RV (eds) New perspectives on games and interaction. Amsterdam University Press, Amsterdam
Vardi MY, Wolper P (1994) Reasoning about infinite computations. Inf Comput 115(1):1–37
Wegener I (2000) Branching programs and binary decision diagrams. SIAM, Philadelphia
Author information
Authors and Affiliations
Corresponding author
Additional information
This is an extended version of the paper “Symbolic Bounded Synthesis”, presented at the 22nd International Conference on Computer Aided Verification (CAV 2011).
This work was supported by the German Research Foundation (DFG) within the program “Performance Guarantees for Computer Systems” and the Transregional Collaborative Research Center “Automatic Verification and Analysis of Complex Systems” (SFB/TR 14 AVACS).
Rights and permissions
About this article
Cite this article
Ehlers, R. Symbolic bounded synthesis. Form Methods Syst Des 40, 232–262 (2012). https://doi.org/10.1007/s10703-011-0137-x
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10703-011-0137-x