Energy-centric DVFS controlling method for multi-core platforms | Computing Skip to main content

Advertisement

Springer Nature Link
Log in

Energy-centric DVFS controlling method for multi-core platforms

  • Published:
Computing Aims and scope Submit manuscript

Abstract

Dynamic voltage and frequency scaling (DVFS) is a well-known and effective technique for reducing energy consumption in modern processors. However, accurately predicting the effect of frequency scaling on system performance is a challenging problem in real environments. In this paper, we propose a realistic DVFS performance prediction method, and a practical DVFS control policy (eDVFS) that aims to minimize total energy consumption in multi-core platforms. We also present power consumption estimation models for CPU and DRAM by exploiting a hardware energy monitoring unit. We implemented eDVFS in Linux, and our evaluation results show that eDVFS can save a substantial amount of energy compared with Linux “on-demand” CPU governor in diverse environments.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
¥17,985 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price includes VAT (Japan)

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10

Similar content being viewed by others

Explore related subjects

Discover the latest articles, news and stories from top researchers in related subjects.

Notes

  1. We use interpolation to calculate the missing points.

References

  1. Carothers NL (2000) Real analysis. Cambridge University Press, Cambridge

    Book  MATH  Google Scholar 

  2. Choi K, Soma R, Pedram M (2004) Dynamic voltage and frequency scaling based on workload decomposition. In: Proceedings of the 2004 international symposium on Low power electronics and design

  3. David H, Fallin C, Gorbatov E, Hanebutte UR, Mutlu O (2011) Memory power management via dynamic voltage/frequency scaling. In: Proceedings of the 8th ACM international conference on Autonomic computing, ICAC ’11. ACM, New York, pp 31–40

  4. Dhiman G, Kontorinis V, Tullsen D, Rosing T, Saxe E, Chew J (2010) Dynamic workload characterization for power efficient scheduling on cmp systems. In: Proceedings of the 16th ACM/IEEE international symposium on low power electronics and design

  5. Eyerman S, Eeckhout L (2010) A counter architecture for online DVFS profitability estimation. IEEE Trans Comput 59(11):1576–1583. doi:10.1109/TC.2010.65

    Article  MathSciNet  Google Scholar 

  6. Google: Google data centers. http://goo.gl/qoOtg

  7. Greenpeace: how dirty is your data? http://goo.gl/QCiKE

  8. Intel: Intel Performance Counter Monitor. http://goo.gl/wsGVr

  9. Intel: Xeon processor e5 family. http://www.intel.com/content/www/us/en/processors/xeon/xeon-processor-5000-sequence.html

  10. Isci C, Martonosi M (2006) Phase characterization for power: evaluating control-flow-based and event-counter-based techniques. In: The twelfth international symposium on high-performance computer architecture, pp 121–132

  11. Keramidas G, Spiliopoulos V, Kaxiras S (2010) Interval-based models for run-time dvfs orchestration in superscalar processors. In: Proceedings of CF. New York. doi:10.1145/1787275.1787338

  12. McVoy L, Staelin C (1996) LMbench—tools for performance analysis. http://www.bitmover.com/lmbench/

  13. Le Sueur E, Heiser G (2010) Dynamic voltage and frequency scaling: the laws of diminishing returns. In: Proceedings of the 2010 international conference on power aware computing and systems

  14. Li C, Qouneh A, Li T (2012) iSwitch: coordinating and optimizing renewable energy powered server clusters. In: Proceedings of the 39th ACM/IEEE international symposium on computer architecture. Portland, OR, USA

  15. Lim H, Kansal A, Liu J (2011) Power budgeting for virtualized data centers. In: Proceedings of the 2011 USENIX conference on USENIX annual technical conference. Berkeley, CA, USA. http://dl.acm.org/citation.cfm?id=2002181.2002186

  16. Ma K, Li X, Chen M, Wang X (2011) Scalable power control for many-core architectures running multi-threaded applications. In: Proceedings of the 38th annual international symposium on Computer architecture. New York. doi:10.1145/2000064.2000117

  17. Micron Technology Inc.: Tn-41-01: calculating memory system power for ddr3. http://www.micron.com/~/media/Documents/Products/Technical%20Note/DRAM/TN41_01DDR3_Power.pdf

  18. Miftakhutdinov R, Ebrahimi E, Patt YN (2012) Predicting performance impact of dvfs for realistic memory systems. In: Proceedings of MICRO-45. Vancouver, BC, Canada

  19. Miller R. The evolution of facebooks data center cooling. http://goo.gl/TFtcG

  20. Rountree B, Lowenthal DK, Schulz M, de Supinski BR (2011) Practical performance prediction under dynamic voltage frequency scaling. Proceedings of IGCC. Washington, DC, USA, In. doi:10.1109/IGCC.2011.6008553

  21. Schöne R, Hackenberg D, Molka D (2012) Memory performance at reduced cpu clock speeds: an analysis of current x86_64 processors. In: Proceedings of HotPower. Berkeley, CA, USA. http://dl.acm.org/citation.cfm?id=2387869.2387878

  22. Sharma N, Barker S, Irwin D, Shenoy P (2011) Blink: managing server clusters on intermittent power. In: Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems, ASPLOS XVI, pp. 185–198. ACM, New York, NY, USA

  23. Sherwood T, Sair S, Calder B (2003) Phase tracking and prediction. In: Proceedings of the 30th annual international symposium on Computer architecture, ISCA ’03, pp 336–349

  24. U.S. Department of Energy: Data center energy consumption trends. http://goo.gl/JcUnU

  25. Weissel A, Bellosa F (2002) Process cruise control: event-driven clock scaling for dynamic power management. In: Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems

  26. Wu Q, Martonosi M, Clark DW, Reddi VJ, Connors D, Wu Y, Lee J, Brooks D (2005) A dynamic compilation framework for controlling microprocessor energy and performance. In: Proceedings of the 38th annual IEEE/ACM international symposium on microarchitecture

Download references

Acknowledgments

This research was supported by Next-Generation Information Computing Development Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (No. 2010-0020731). The ICT at Seoul National University provided research facilities for this study.

Author information

Authors and Affiliations

  1. School of Computer Science and Engineering, Seoul National University, Seoul, Korea

    Shin-gyu Kim, Hyeonsang Eom, Heon Y. Yeom & Sang Lyul Min

Authors
  1. Shin-gyu Kim
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Hyeonsang Eom
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Heon Y. Yeom
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Sang Lyul Min
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Heon Y. Yeom.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Kim, Sg., Eom, H., Yeom, H.Y. et al. Energy-centric DVFS controlling method for multi-core platforms. Computing 96, 1163–1177 (2014). https://doi.org/10.1007/s00607-013-0369-2

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00607-013-0369-2

Keywords

Mathematics Subject Classification

Search

Navigation