FPGA based low power hardware for quality access control of compressed gray scale image | Microsystem Technologies
Skip to main content
Springer Nature Link
Log in

FPGA based low power hardware for quality access control of compressed gray scale image

  • Technical Paper
  • Published:
Microsystem Technologies Aims and scope Submit manuscript

Abstract

This paper proposes novel hardware architecture of passive data-hiding scheme for quality access control of digital image in discrete cosine transform compressed domain. Both serial and parallel hardware implementation are done and a comparative detail model’s performance is reported. Passive data hiding is a technique used for media identification where it is expected that signal distortions caused due to data hiding can be reverted by the authorized user to enjoy the full quality. The main objectives of hardware assisted passive data hiding are to achieve low power usage, reliability, real-time performance, and ease of integration with existing consumer electronic devices. The proposed architecture is synthesized using Xilinx’s ISE for a field-programmable gate array and also tested over large number of benchmark images. It is seen that (a) in real time processing, the scheme saves 90.42% power than the related implementation found in the literature, (b) a very high throughput of 11.37 and 11.41 Mb/s are achieved with parallel implementation for access control encoder and decoder, respectively at a maximum operating frequency of 111.03 MHz for an image of size (512 × 512). Obtained experimental results are also compared with related schemes and found to be superior.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
¥17,985 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price includes VAT (Japan)

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14

Similar content being viewed by others

References

  • Ali MO, Osman EAAA, Row R (2012) Invisible digital image watermarking in spatial domain with random localization. Int J Eng Innov Technol 2:227–231 (ISSN: 2277-3754)

    Google Scholar 

  • Chang FC, Huang HC, Hang HM (2007) Layered access control schemes on watermarked scalable media. J VLSI Signal Process Syst Signal Image Video Technol 49:443–455. https://doi.org/10.1007/s11265-007-0095-0

    Article  Google Scholar 

  • Chatterjee N, Sohid M, Chakraborty S (2013) VLSI architecture of spread sprectrum image watermarking decoder. In: Proceedings of international conference on advances in computing vol 16, pp 51–658

  • Chen WH, Smith CH, Fralick S (1977) A Fast computational algorithm for the discrete cosine transform. IEEE Trans Commun 25:1004–1009. https://doi.org/10.1109/TCOM.1977.1093941

    Article  MATH  Google Scholar 

  • Chen JR, Chao PCP, Tsai CH, Chen WD (2014) Design and realization of a high resolution (640 × 480) SWIR image acquisition system. Microsyst Technol 28:1583–1595. https://doi.org/10.1007/s00542-014-2179-7

    Article  Google Scholar 

  • Darji AD, Lad TC, Merchant SN, Chandorkar AN (2013) Watermarking hardware based on wavelet coefficients quantization method. Circuits Syst Signal Process 32:2559–2579. https://doi.org/10.1007/s00034-013-9550-2

    Article  MathSciNet  Google Scholar 

  • Ghosh S, Das N, Das S, Maity SP, Rahaman H (2015) An adaptive feedback based reversible watermarking algorithm using difference expansion. In: Proceedings of 2nd international conference on recent trends in information systems (ReTIS) vol 1, pp 207–212. https://doi.org/10.1109/retis.2015.7232879

  • Grosbois R, Gerbelot P, Ebrahimi T (2001) Authentication and access control in the jpeg 2000 compressed domain. In: Proceedings of SPIE 46th annual meeting, applications of digital image processing vol 1, pp 95–104. https://doi.org/10.1117/12.449744

  • Hazra S, Ghosh S, De S, Rahaman H (2017) FPGA implementation of semi-fragile reversible watermarking by histogram bin shifting in real time. J Real-Time Image Process 1:1–29. https://doi.org/10.1007/s11554-017-0672-9

    Article  Google Scholar 

  • Hsien S, Lee SJ (2003) A JPEG chip for image compression and decompression. J VLSI Signal Process 35:43–60. https://doi.org/10.1023/A:1023383820503

    Article  MATH  Google Scholar 

  • Imaizumi S, Watanabe O, Fujiyoshi M, Kiya H (2005) Generalized hierarchical encryption of JPEG 2000 codestreams for access control. In: Proceeding of IEEE international conference on image processing 2005 II:1094-1097. https://doi.org/10.1109/icip.2005.1530250

  • Joshi A, Mishra V, Patrikar R (2015) Real time implementation of integer DCT based video watermarking architecture. Int Arab J Inf Technol 12:741–747

    Google Scholar 

  • Joshi AM, Mishra V, Patrikar RM (2016a) FPGA prototyping of video watermarking for ownership verification based on H. 264/AVC. Multimed Tools Appli 75:3121–3144. https://doi.org/10.1007/s11042-014-2426-z

    Article  Google Scholar 

  • Joshi VB, Raval MS, Gupta D, Rege PP, Parulkar SK (2016b) A multiple reversible watermarking technique for fingerprint authentication. Multimed Syst 22:367–378. https://doi.org/10.1007/s00530-015-0465-6

    Article  Google Scholar 

  • Kaddachi ML, Soudani A, Lecuire V, Torki K, Makkaoui L, Moureaux JM (2012) Low power hardware-based image compression solution for wireless camera sensor networks. Comput Stand Interfac 34:14–23. https://doi.org/10.1016/j.csi.2011.04.001

    Article  Google Scholar 

  • Kitsos P, Voros NS, Dagiuklas T, Skodras AN (2013) A high speed FPGA implementation of the 2D DCT for ultra high definition video coding. In: Proceedings of 18th international conference on digital signal processing (DSP) vol 1, pp 1–5. https://doi.org/10.1109/icdsp.2013.6622742

  • Lin SL, Huang CF, Liou MH, Chen CY (2013) Improving histogram-based Reversible information hiding by an optimal weight-based prediction scheme. J Inf Hiding Multimed Signal Process 4:19–33 (ISSN 2073-4212 )

    Google Scholar 

  • Maity SP, Kundu MK (2013) Distortion free image-in-image communication with implementation in FPGA. AEU-Int J Electr Commun 67:438–447. https://doi.org/10.1016/j.aeue.2012.10.014

    Article  Google Scholar 

  • Maity HK, Maity SP (2014) FPGA implementation of reversible watermarking in digital image using reversible contrast mapping. J Syst Softw 96:93–104. https://doi.org/10.1016/j.jss.2014.05.079

    Article  Google Scholar 

  • Maity SP, Kundu M, Maity S (2009) Dual purpose FWT domain spread spectrum image watermarking in real time. Int J Comput Electr Eng 35:415–433. https://doi.org/10.1016/j.compeleceng.2008.06.003

    Article  MATH  Google Scholar 

  • Mandal H, Maity GK, Phadikar A, Chiu TL (2017) FPGA based low power hardware implementation for quality access control of a compressed gray scale image. In: Proceedings of first international conference on computational intelligence, communications, and business analytics (CICBA), communications in computer and information science, Springer, Singapore vol 775, pp 416–430

  • Mohanty SP, Ranganathan N, Balakrishnan K (2006) A dual voltage-frequency VLSI chip for image watermarking in DCT domain. IEEE Trans Circuits Syst II Express Briefs 53:394–398. https://doi.org/10.1109/TCSII.2006.870216

    Article  Google Scholar 

  • Mohanty SP, Kougianos E, Ranganathan N (2007) VLSI architecture and chip for combined invisible robust and fragile watermarking. IET Comput Digit Tech 1:600–611. https://doi.org/10.1049/iet-cdt:20070057

    Article  Google Scholar 

  • Phadikar A, Maity SP (2010) Quality access control of compressed color images using data hiding. AEU-Int J Electr Commun 64:833–843. https://doi.org/10.1016/j.aeue.2009.09.004

    Article  Google Scholar 

  • Phadikar A, Kundu MK, Maity SP (2008) Quality access control of a compressed gray scale image. In: Proceeding of computer vision, pattern recognition, image processing and graphics vol 1, pp 13–19

  • Phadikar A, Maity SP, Claude Delpha (2012) Image error concealment and quality access control based on data hiding and cryptography. J Telecommun Syst 49:239–254. https://doi.org/10.1007/s11235-010-9371-6

    Article  Google Scholar 

  • Phadikar A, Mandal H, Maity G, Chiu TL (2015) A new model of QIM data hiding for quality access control of digital image. In: Proceedings of IEEE international conference on soft-computing and networks security (ICSNS) vol 1, pp 1–5. https://doi.org/10.1109/icsns.2015.7292441

  • Shete KS, Patil M, Chitode JS (2016) Least significant bit and discrete wavelet transform algorithm realization for image steganography employing FPGA. Int J Image Gr Signal Process 8:48. https://doi.org/10.5815/ijigsp.2016.06.06

    Article  Google Scholar 

  • Wang Z, Bovik AC, Sheikh HR, Simoncelli EP (2004) Image quality assessment: from error measurement to structural similarity. IEEE Trans Image Process 13:600–612. https://doi.org/10.1109/TIP.2003.819861

    Article  Google Scholar 

  • Wu X, Hu J, Gu Z, Huang J (2005) A secure semi-fragile watermarking for image authentication based on integer wavelet transform with parameters. In: Proceeding of the 2005 Australian workshop on grid computing and e-research vol 1, pp 75–-80. ISBN:1-920-68226-0

  • Zhang J, Liu L (2017) Publicly verifiable watermarking for intellectual property protection in FPGA design. IEEE Trans Very Large Scale Integr VLSI Syst 25:1520–1527. https://doi.org/10.1109/TVLSI.2016.2619682

    Article  Google Scholar 

Download references

Acknowledgements

The authors would like to thank the Ministry of Science and Technology (MOST), Taiwan R.O.C., under grant number MOST 106-3113-E-155-001-CC2, 105-3113-E-155-001, 104-3113-E-155-001, 103-3113-E-155-001, 103-2221-E-155-028-MY3 for their kind funding.

Author information

Authors and Affiliations

  1. Department of Photonics Engineering, Yuan Ze University, Taoyuan, Taiwan

    Himadri Mandal & Tien-Lung Chiu

  2. Department of Information Technology, MCKV Institute of Engineering, Liluah, Howrah, West Bengal, India

    Amit Phadikar

  3. Department of Physics, Pingla Thana Mahavidyalaya, Maligram, Paschim Medinipur, West Bengal, India

    Goutam Kr. Maity

Authors
  1. Himadri Mandal
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Amit Phadikar
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Goutam Kr. Maity
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Tien-Lung Chiu
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Amit Phadikar.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Mandal, H., Phadikar, A., Maity, G.K. et al. FPGA based low power hardware for quality access control of compressed gray scale image. Microsyst Technol 28, 433–446 (2022). https://doi.org/10.1007/s00542-018-3817-2

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00542-018-3817-2

Search

Navigation