Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach

Das, Subhajit; Ghosh, Sudip; Das, Nachiketa; Maity, Santi P.; Rahaman, Hafizur; Maity, Reshmi; Maity, Niladri

doi:10.1007/s00034-018-0979-1

Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach

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Published: 12 November 2018

Volume 37, page 5690, (2018)
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Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach

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Subhajit Das¹,
Sudip Ghosh³,
Nachiketa Das⁴,
Santi P. Maity⁵,
Hafizur Rahaman⁵,
Reshmi Maity² &
…
Niladri Maity²

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The Original Article was published on 21 July 2017

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1 Correction to: Circuits, Systems, and Signal Processing (2018) 37:1575–1593 https://doi.org/10.1007/s00034-017-0609-3

The original version of the article unfortunately contained an error in the author group. Four authors were not included in the original version.

Dr. Sudip Ghosh, Dr. Nachiketa Das, Dr. Santi P. Maity and Dr. Hafizur Rahaman are newly included as second, third, fourth and fifth authors in the author group. Dr. Reshmi Maity and Dr. Niladri Maity are now listed as sixth and seventh authors in the author group.

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Authors and Affiliations

Department of Electronics and Communication Engineering, National Institute of Technology, Aizawl, 796 012, India
Subhajit Das
Department of Electronics and Communication Engineering, Mizoram University, Aizawl, 796 004, India
Reshmi Maity & Niladri Maity
School of VLSI Technology, Indian Institute of Engineering Science & Technology (IIEST), Shibpur, Howrah, West Bengal, 711 103, India
Sudip Ghosh
Indian Maritime University, Kolkata Campus, Kolkata, 700 088, India
Nachiketa Das
Department of Information Technology, Indian Institute of Engineering Science & Technology (IIEST), Shibpur, Howrah, West Bengal, 711 103, India
Santi P. Maity & Hafizur Rahaman

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Subhajit Das
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Sudip Ghosh
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Nachiketa Das
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Santi P. Maity
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Hafizur Rahaman
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Reshmi Maity
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Niladri Maity
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Correspondence to Niladri Maity.

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Das, S., Ghosh, S., Das, N. et al. Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach. Circuits Syst Signal Process 37, 5690 (2018). https://doi.org/10.1007/s00034-018-0979-1

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Published: 12 November 2018
Issue Date: December 2018
DOI: https://doi.org/10.1007/s00034-018-0979-1

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Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach

1 Correction to: Circuits, Systems, and Signal Processing (2018) 37:1575–1593 https://doi.org/10.1007/s00034-017-0609-3

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