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Set-Reset Flip-Flop Circuit with a Simple Output Logic

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Abstract

The equation of the plane (EOP) in analytic geometry is used to build a logic dynamic architecture, i.e., a combination of set-reset flip-flop (SR-FF) and basic logic gates. This is achieved by using two of the variables in the EOP as the input signals of the SR-FF and the remaining variable as the output signal. This theoretical proposal for mixing the SR-FF and the basic logic gates is confirmed experimentally by means of a simple electronic implementation.

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References

  1. D. Cafagna, G. Grassi, Chaos-based SR Flip-Flop via Chua’s circuit. Int. J. Bifurc. Chaos 16, 1521–1526 (2006)

    Article  Google Scholar 

  2. I. Campos-Cantón, E. Campos-Cantón, J.A. Pecina-Sanchez, H.C. Rosu, A simple circuit with dynamic logic architecture of basic logic gates. Int. J. Bifurc. Chaos 20, 2547–2551 (2010)

    Article  Google Scholar 

  3. F. Chen, W. Tang, G. Chen, Single-layer perceptron and dynamic neuron implementing linearly non-separable Boolean functions. Int. J. Circuit Theory Appl. 37, 433–451 (2009)

    Article  MathSciNet  Google Scholar 

  4. W.L. Ditto, A. Miliotis, K. Murali, S. Sinha, M.L. Spano, Chaogates: morphing logic gates that exploit dynamical patterns. Chaos 20, 037107 (2010)

    Article  MathSciNet  Google Scholar 

  5. D. Kuo, Chaos and its computing paradigm. IEEE Potentials 24, 13–15 (2005)

    Article  Google Scholar 

  6. T. Munakata, S. Sinha, W. Ditto, Chaos computing: implementation of fundamental logical gates by chaotic elements. IEEE Trans. Circuits Syst. I, Fundam. Theory Appl. 49, 1629–1633 (2002)

    Article  MathSciNet  Google Scholar 

  7. K. Murali, A. Miliotis, W.L. Ditto, S. Sinha, Logic from nonlinear dynamical evolution. Phys. Lett. A 373, 1346–1351 (2009)

    Article  MathSciNet  MATH  Google Scholar 

  8. K. Murali, S. Sinha, W.L. Ditto, Implementation of NOR gate by a chaotic Chua’s circuit. Int. J. Bifurc. Chaos 13, 2669–2672 (2003)

    Article  MATH  Google Scholar 

  9. K. Murali, S. Sinha, W.L. Ditto, A.R. Bulsara, Reliable logic circuit elements that exploit nonlinearity in the presence of a noise floor. Phys. Rev. Lett. 102, 104101 (2009)

    Article  Google Scholar 

  10. K. Murali, S. Sinha, I.R. Mohamed, Chaos computing: experimental realization of NOR gate using a simple chaotic circuit. Phys. Lett. A 339, 39–44 (2005)

    Article  MATH  Google Scholar 

  11. T. Roska, Circuits, computers, and beyond Boolean logic. Int. J. Circuit Theory Appl. 35, 485–496 (2007)

    Article  MATH  Google Scholar 

  12. A. Shinya, S. Mitsugi, T. Tanabe, M. Notomi, I. Yokohama, All-optical flip-flop circuit composed of coupled two-port resonant tunneling filter in two-dimensional photonic crystal slab. Opt. Express 14, 1230–1235 (2006)

    Article  Google Scholar 

  13. S. Sinha, W. Ditto, Dynamics based computations. Phys. Rev. Lett. 81, 2156–2159 (1998)

    Article  Google Scholar 

  14. S. Sinha, W. Ditto, Computing with distributed chaos. Phys. Rev. E 60, 363–377 (1999)

    Article  Google Scholar 

  15. S.L. Yan, Chaotic synchronization of two inverse-injection semiconductor lasers for logic gates. Opt. Rev. 18, 42–46 (2011)

    Article  Google Scholar 

Download references

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Authors and Affiliations

  1. Facultad de Ciencias, Universidad Autónoma de San Luis Potosí, Alvaro Obregón 64, 78000, San Luis Potosí, SLP, Mexico

    I. Campos-Cantón & E. Castellanos-Velasco

  2. IPICyT, Instituto Potosino de Investigacion Cientifica y Tecnologica, Camino a la Presa San José 2055, Col. Lomas 4a sección, C.P. 78216, San Luis Potosí, SLP, Mexico

    E. Campos-Cantón & H. C. Rosu

Authors
  1. I. Campos-Cantón
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  2. E. Campos-Cantón
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  3. H. C. Rosu
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  4. E. Castellanos-Velasco
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Corresponding author

Correspondence to H. C. Rosu.

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Campos-Cantón, I., Campos-Cantón, E., Rosu, H.C. et al. Set-Reset Flip-Flop Circuit with a Simple Output Logic. Circuits Syst Signal Process 31, 753–760 (2012). https://doi.org/10.1007/s00034-011-9343-4

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  • DOI: https://doi.org/10.1007/s00034-011-9343-4

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