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FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction

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Abstract

Functional verification techniques based on fault injection and simulation at register-transfer level (RTL) have been largely investigated in the past years. Although they have various advantages such as scalability and simplicity, they commonly suffer from the low speed of the cycle-accurate RTL simulation. On the other hand, Transaction-level modeling (TLM) allows a simulation speed sensibly faster than RTL. This article presents FAST, a framework to accelerate RTL fault simulation through automatic RTL-to-TLM abstraction. FAST abstracts RTL models injected with any RTL fault model into equivalent injected TLM models thus allowing a very fast fault simulation at TLM level. The article also presents FAST-DT, a new bit-accurate data type library integrated in the framework that allows a further improvement of the simulation speed-up. Finally, the article shows how the generated TLM test patterns can be automatically synthesized into RTL test patterns by exploiting the structural information of the RTL model extracted during the abstraction process. Experimental results have been performed on several designs of different size and complexity to show the methodology effectiveness.

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References

  1. Ara K, Suzuki K (2003) A proposal for transaction-level verification with component wrapper language. In: Proc. of ACM/IEEE DATE, pp 82–87

  2. Armstrong JR, Lam FS, Ward PC (1992) Test Generation and Fault Simulation for Behavioral Models. Prentice Hall

  3. Bombieri N, Fummi F, Pravadelli G (2006) On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL. In: Proc. of ACM/IEEE DATE, vol 1, pp 1–6

  4. Bombieri N, Fummi F, Pravadelli G (2007) Incremental ABV for functional validation of TL-to-RTL design refinement. In: Proc. of ACM/IEEE DATE, pp 882–887

  5. Bombieri N, Fummi F, Pravadelli G, Marques-Silva J (2007) Towards equivalence checking between TLM and RTL models. In: Proc. of ACM/IEEE MEMOCODE, pp 113–122

  6. Bombieri N, Fummi F, Pravadelli G, Hampton M, Letombe F (2009) Functional qualification of TLM verification. In: Proc. of ACM/IEEE DATE, pp 190–195

  7. Bombieri N, Fummi F, Guarnieri V (2011) Accelerating RTL fault simulation through RTL-to-TLM abstraction. In: Proc. of IEEE ETS, pp 117–122

  8. Bombieri N, Fummi F, Pravadelli G (2011) Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions. IEEE Trans Comput 60(12):1730–1743

    Article  MathSciNet  Google Scholar 

  9. Borgatti M, Capello A, Rossi U, Lambert GL, Moussa I, Fummi F, Pravadelli G (2005) An integrated design and verification methodology for reconfigurable multimedia system. In: Proc. of ACM/IEEE DATE, pp 266–271

  10. Cai L, Gajski D (2003) Transaction level modeling: an overview. In: Proc. of ACM/IEEE CODES+ISSS, pp 19–24

  11. Cheng K-T, Krishnakumar A (1996) Automatic generation of functional vectors using the extended finite state machine model. ACM TODAES 1(1):57–79

    Article  Google Scholar 

  12. Corno F, Cumani G, Sonza-Reorda M, Squillero G (2000) RT-level fault simulation techniques based on simulation command scripts. In: Proc. of IEEE DCIS, pp 21–24

  13. Deniziak S, Sapiecha K (2004) Fast high-level fault simulator. In: Proc. of IEEE ICECS, pp 583–586

  14. Dongwoo L, Jongwhoa N (2009) A novel simulation fault injection method for dependability analysis. IEEE Des Test Comput 26(6):50–61

    Article  Google Scholar 

  15. Donlin A (2004) Transaction level modeling: Flows and use models. In: Proc. of ACM/IEEE CODES + ISSS, pp 75–80

  16. Ecker W, Esen V, Schonberg L, Steininger T, Velten M, Hull M (2007) Impact of description languages, abstraction layer, and value representation on simulation performance. In: Proc. of ACM/IEEE DATE, pp 767–772

  17. Ferrandi F, Fummi F, Pravadelli G, Sciuto D (2003) Identification of design errors through functional testing. IEEE Trans Reliab 52(4):400–412

    Article  Google Scholar 

  18. Ghenassia F, Clouard A, Jain K, Maillet-Contoz L, Strassen J-P (2003) Using Transactional Level Models in a SoC Design Flow. Kluwer Academic Publishers

  19. Ghosh I, Fujita M (2001) Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams. IEEE Trans Comput-Aided Des Integr Circuits Syst 20(3):401–415

    Article  Google Scholar 

  20. Gracia J, Baraza JC, Gil D, Gil PJ (2001) Comparison and application of different VHDL-based fault injection techniques. In: Proc. of IEEE DFT, pp 579–582

  21. Guerrouat A, Richter H (2006) A component-based specification approach for embedded systems using FDTs. ACM SIGSOFT Softw Eng Notes 31(2):14–18

    Article  Google Scholar 

  22. Kammler D, Ascheid GJG, Leupers R, Meyr H (2009) A fast and flexible platform for fault injection and evaluation in Verilog-based simulations. In: Proc. of IEEE SSIRI, pp 309–314

  23. Katagiri H, Yasumoto K, Kitajima A, Higashino T, Taniguchi K (2000) Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization. In: Proc. of ACM/IEEE DAC, pp 762–767

  24. Koo TJ, Sinopoli B, Sangiovanni-Vincentelli A, Sastry S (1999) A formal approach to reactive system design: unmanned aerial vehicle flight management system design example. In: Proc. of IEEE CACSD, pp 522–527

  25. Liang Z, Ghosh I, Hsiao M (2006) A framework for automatic design validation of RTL circuits using ATPG and observability-enhanced tag coverage. IEEE Trans Comput-Aided Des Integr Circuits Syst 25(11):2526–2538

    Article  Google Scholar 

  26. Mao W, Gulati RK (1996) Improving gate level fault coverage by RTL fault grading. In: Proc. of IEEE ITC, p 150

  27. Mingsong C, Mishra P, Kalita D (2007) Towards RTL test generation from SystemC TLM specifications. In: Proc. of IEEE HLDVT, pp 91–96.

  28. Park S, Chen L, Parvathala PK, Patil S, Pomeranz I (2006) A functional coverage metric for estimating the gate-level fault coverage of functional tests. In: Proc. of IEEE ITC, pp 1–10

  29. Rimen M, Ohlsson J, Jenn E, Arlat J, Karlsson J (1994) Fault injection into VHDL models: the MEFISTO tool. In: Proc. of IEEE FTCS, pp 66–75

  30. Su M-Y, Shih C-H, Huang J-D, Jou J-Y (2006) FSM-based transaction-level functional coverage for interface compliance verification. In: Proc. of ACM/IEEE ASP-DAC, pp 448–453

  31. Takach A, Gutberlet P, Waters S (2004) Fast bit-accurate C+ + datatypes for functional system verification and synthesis. In: Proc. of ECSI FDL, pp 337–345

  32. Thaker P, Agrawal V, Zaghloul M (2003) A test evaluation technique for VLSI circuits using register-transfer level fault modeling. IEEE Trans Comput-Aided Des Integr Circuits Syst 22(8):1104–1113

    Article  Google Scholar 

  33. TLM-2.0 (2009) OSCI TLM-2.0 Language Reference Manual, Open SystemC Organization Initiative, http://www.accellera.org/downloads/standards/. Accessed 5 July 2012

  34. Tschche O, Sieh V, Balbach F (1997) VERIFY: Evaluation of reliability using VHDL-models with embedded fault descriptions. In: Proc. of IEEE FTCS, pp 32–36

  35. Wang Z-H, Ye Y-Z (2005) The improvement for transaction level verification functional coverage. In: Proc. of IEEE ISCAS, pp 5850–5853

  36. Zhong-hai W, Yi-zheng Y (2005) The improvement for transaction level verification functional coverage. In: Proc. of IEEE ISCAS, pp 5850–5853

  37. Zitouni A, Badrouchi S, Tourki R (2006) Communication architecture synthesis for multi-bus SoC. JCS 2(1):63–71

    Google Scholar 

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Authors and Affiliations

  1. Department of Computer Science, University of Verona, Verona, Italy

    Nicola Bombieri, Franco Fummi & Valerio Guarnieri

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  1. Nicola Bombieri
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  2. Franco Fummi
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  3. Valerio Guarnieri
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Correspondence to Nicola Bombieri.

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Responsible Editor: C. Metra

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Bombieri, N., Fummi, F. & Guarnieri, V. FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction. J Electron Test 28, 495–510 (2012). https://doi.org/10.1007/s10836-012-5318-z

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  • DOI: https://doi.org/10.1007/s10836-012-5318-z

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