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Data prefetching for digital alpha

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High-Performance Computing and Networking (HPCN-Europe 1999)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1593))

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Abstract

Some of the current microprocessors provide a prefetch instruction, but either the instruction is treated as a NOP, (e.g. Digital Alpha EV4/5), or only a small number of outstanding prefetches is permitted (e.g. MIPS R10K). This paper discusses the design and implementation of the hardware support required to fully support the prefetch instruction for the Digital Alpha architecture. The prefetch support is implemented in a cycle-level functional simulator of the Alpha architecture.

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References

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Author information

Authors and Affiliations

  1. Department of Computer Science, University of Auckland, New Zealand

    S. Manoharan

Authors
  1. S. Manoharan
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Editor information

Peter Sloot Marian Bubak Alfons Hoekstra Bob Hertzberger

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© 1999 Springer-Verlag

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Manoharan, S. (1999). Data prefetching for digital alpha. In: Sloot, P., Bubak, M., Hoekstra, A., Hertzberger, B. (eds) High-Performance Computing and Networking. HPCN-Europe 1999. Lecture Notes in Computer Science, vol 1593. Springer, Berlin, Heidelberg . https://doi.org/10.1007/BFb0100678

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  • DOI: https://doi.org/10.1007/BFb0100678

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-65821-4

  • Online ISBN: 978-3-540-48933-7

  • eBook Packages: Springer Book Archive

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