A co-simulation concept for an efficient analysis of complex logic designs

Abstract

The focus of this paper is the presentation of our work on developing a novel co-simulation concept for synchronous logic designs. The growing complexity of programmable devices (FPGAs and CPLDs) requires complex test environments to find design and implementation errors as early in the design process as possible. In most cases it is the system environment that determines the performance requirements of the design and its behavior under dynamic workloads. Our approach takes advantage of the fact that the circuit design and simulation can be implemented with standard hardware description languages (HDLs). To model and simulate the system environment, however, we have used a state-of-the-art simulation language. Both simulations are tied together through a simple communication structure. The simulators constantly exchange state information, which provides dynamic feedback to simulate realistic workloads. As an application example we will describe how this concept was applied during the development of the controller logic for an optical high-speed network adapter.