Abstract
This paper is devoted to VLSI implementation of a staged decoder for Block-Coded Modulation (BCM). We first review a general parallel and pipelined implementation of the decoder and we identify the parameters to be considered for optimization. A particular BCM scheme, based on the 8-PSK signal set, is chosen for a case study. Several ideas are described leading to a code-optimized design, and hardware implementation is shown. Next, we evaluate the performance of our design. In particular it is shown that, by exploiting regularity, a simple structure which achieves a throughput rate of 10 Mbps can be implemented by using 23 K transistors and 2Μ standard cells CMOS technology. Further optimization and simple stacking of ten processors on a single chip in a block-processing structure allows us to achieve a throughput rate of 100 Mbps with about 150 K transistors (38 K gates).
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
Abbreviations
- AWGN:
-
Additive White Gaussian Noise Channel
- BCM:
-
Block-Coded Modulation
- CP:
-
Comparator Processor
- DG:
-
Dependence Graph
- ED:
-
Euclidean Distance
- HD:
-
Hamming Distance
- MAC:
-
Multiply-and-Accumulate
- MXC:
-
Multiplex-and-Accumulate
- ML:
-
Maximum Likelihood
- PE:
-
Processing Element
- PSK:
-
Phase-Shift Keying
- SD:
-
Staged Decoder
- SFG:
-
Signal Flow Graph
- TCM:
-
Trellis-Coded Modulation
- VA:
-
Viterbi Algorithm
References
E. Biglieri, D. Divsalar, P.J. McLane, and M.K. Simon,Introduction to Trellis-Coded Modulation with Applications, New York: Macmillan, 1991.
G. Ungerboeck, “Channel Coding with Multilevel/Phase Signals,”IEEE Trans. Inform. Th., Vol. IT-28, pp. 56–67, January 1982.
G.D. Forney, “The Viterbi Algorithm,”Proc. IEEE, Vol. 3, No. 73, pp. 268–78.
V.V. Ginzburg, “Mnogomerniye signaly dlya nepreryvnogo kanala,” (in Russian),Problemy Peredachi Informatsii, pp. 28–46, January–March 1984. English Translation: “Multidimensional Signals for a Continuous Channel,”Problems of Information Transmission, Vol. 23, No. 4, pp. 20–34, January–March 1984.
H. Imai and S. Hirakawa, “A New Multilevel Coding Method Using Error Correcting Codes,”IEEE Trans. Inform. Th., Vol. IT-23, pp. 371–377, 1977.
T. Kasami, T. Takata, T. Fujiwara, and S. Lin, “On Multilevel Block Modulation Codes,”IEEE Trans. on Inform. Th., Vol. 37, No. 4, July 1991.
L.-F. Wei, “Block-CodedM-DPSK with Built-in Time Diversity for Fading Channels,” Submitted toIEEE Transactions on Information Theory, May 1991.
E. Biglieri, “Parallel Demodulation of Multidimensional Signals,”IEEE Trans. on Commun., to be published, 1992.
E. Biglieri and K. Yao, “VLSI Decoder Architectures for Generalized Concatenated Codes,”Proceedings of the Second International Workshop on DSP Techniques Applied to Space Communications, Torino, Italy, 24–25 September, 1990.
S.Y. Kung,VLSI Array Processors, Englewood Cliffs, NJ: Prentice-Hall, 1988.
E.L. Blokh and V.V. Zyablov,Lineinye Kaskadnye Kody (Linear Concatenated Codes). Moskow (Soviet Union), Izdatel'stvo “Nauka,” 1982.
V.A. Zinov'ev, “Generalized cascade codes,”Problems of Information Transmission, Vol. 12, pp. 5–15, January–March 1976.
S.L. Sayegh, “A Class of Optimum Block Codes in the Signal Space,”IEEETrans. on Comm., Vol. COM-34, pp. 1043–1045, October 1986.
R.B. Urquhart and D. Wood, “Systolic Matrix and Vector Multiplication Methods for Signal Processing,”IEE Proc., Vol. 131, pt. F, pp. 623–631, Oct. 1984.
C.L. Wang, C.H. Wei, and S.H. Chen, “Efficient Bit-Level Systolic Array Implementation of FIR and IIR Digital Filters,”IEEE Journal on Selected Areas in Communications, Vol. 6, No. 3, April 1988.
“Scalable CMOS standard cell Library, version 2.0,”Institute for Technology Development, Starkville, Mississippi.
G. Fettweis and H. Meyr, “High-Rate Viterbi Processor: a Systolic Array Solution,”IEEE Journal on Selected Areas in Communications, Vol. 8, No. 8, October 1990.
C.-Y. Chang and K. Yao, “Systolic Array Processing of the Viterbi Algorithm,”IEEE Trans. on Inform., Th., Vol. 35, No. 1, January 1989.
G. Fettweis and H. Meyr, “High-Speed Parallel Viterbi Decoding: Algorithm and VLSI Architecture,”IEEE Communication Magazine, May 1991.
G. Fettweis and H. Meyr, “Feedforward Architectures for Parallel Viterbi Decoding,”Journal of VLSI Signal Processing, Vol. 3, pp. 105–119, 1991.
G.D. Forney, Jr., “Coset codes—Part II: Binary lattices and related codes,”IEEE Trans. Inform. Theory, Vol. 34, No. 5, pp. 1152–1187, September 1988.
T. Kasami, T. Takata, T. Fujiwara, and S. Lin, “A Concatenated Coded Modulation Scheme for Error Control,”IEEE Trans. on Comm., Vol. 38, No. 6, June 1990.
C.-C. Lu and S.-H. Huang, “On trellis-oriented generator matrices,”Proceedings of the International Symposium on Communications, pp. 80–83, December 9–13, Tainan, Taiwan, 1992.
J.K. Wolf, “Efficient Maximum Likelihood Decoding of Linear Block Codes Using a Trellis,”IEEE Trans. on Inform. Th., Vol. 24, No. 1, January 1978.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Caire, G., Ventura-Traveset, J., Murphy, J. et al. Parallel and pipelined VLSI implementation of a staged decoder for BCM signals. Journal of VLSI Signal Processing 11, 195–211 (1995). https://doi.org/10.1007/BF02107053
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/BF02107053