Cellular array processor CAP and applications | Journal of Signal Processing Systems Skip to main content
Log in

Abstract

The general-purpose, highly parallel, cellular array processor (CAP) we developed features multiple-instruction stream, multiple-data stream (MIMD) processing and image display. Processor elements can number in several hundreds. The present system uses 256 processors. Each processor element consists of a general-purpose microprocessor, memory, and a special VLSI chip that performs parallel-processing-specific functions such as processor communication and synchronization. The VLSI has two 2M byte/s independent common bus interfaces for data broadcating and six 15M bit/s serial communication ports for local data communication. The chip also can process image data in real time for multiple processors. Use of the communication interfaces enables a variety of processor networks to be configured. One CAP application has been computer graphics, in which ray tracing is used to generate quality images.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Subscribe and save

Springer+ Basic
¥17,985 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price includes VAT (Japan)

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. Intel Corp., data sheets.

  2. W.D. Hillis,The Connection Machine, Cambridge, Mass.: MIT Press, 1985.

    Google Scholar 

  3. J.D. Hayes,et al., “Architecture of a Hypercube Supercomputer”,Proc. Int'l conf. on Parallel Processing, 1986, pp. 653–660.

  4. H. Sato, M. Ishii, et al., “Fast Image Generation of Constructive Solid Geometry Using a Cellular Array Processor,”Computer Graphics, 22(2), July 1985, pp. 95–102.

    Article  Google Scholar 

  5. K. Murakami, H. Sato,et al., “Ray Tracing Using Cellular Array Processor CAP” (in Japanese),Information Processing Technical Report, vol. 96, no. 43, CAD-22-2, July 1986.

  6. H. Ishihata, M. Ishii,et al., “VLSI for the Cellular Array Processor”,Proc. Int'l Conf. on Computer Design, 1987, pp. 320–323.

  7. H. Takahashi, et al., “A 240K Transistor CMOS Array with Flexible Allocation of Memory and Channels,”IEEE Journal of Solid State Circuits, vol. SC-20, no. 5, 1985, pp. 1012–1017.

    Article  Google Scholar 

  8. T. Whitted, “An Improved Illumination Model for Shaded Display,”Comm. ACM, vol. 23, no. 6, 1980, pp. 343–349.

    Article  Google Scholar 

  9. “IMS T412 Transputer Reference Manual,” INMOS LTD., Nov. 1984.

  10. K.E. Batcher, “Design of a massively parallel processor,”IEEE Trans. on Comput., vol. C-29, no. 9, Sept. 1980, pp. 836–840.

    Article  Google Scholar 

  11. H.T. Kung, “Why Systolic Architecture?,IEEE Computer, vol. 15, no. 1, Jan. 1982, pp 37–46.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

About this article

Cite this article

Ishii, M., Sato, H., Ikesaka, M. et al. Cellular array processor CAP and applications. J VLSI Sign Process Syst Sign Image Video Technol 1, 57–67 (1989). https://doi.org/10.1007/BF00932066

Download citation

  • Received:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF00932066

Keywords

Navigation