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A characterization of robust test-pairs for stuck-open faults

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Abstract

Tests for stuck-open faults in static CMOS circuits consist of a sequence of two input vectors. Such test-pairs may be invalidated by delays in the circuit. Test-pairs that are not invalidated by delays in the circuit are known as robust test-pairs. We present a six-valued logic system Ω = {0, 1, r, f, 0h, 1h}. We show how Ω differs from a number of other logic systems that have been proposed for test generation. This logic system abstracts the important aspects of the transition behavior of the circuit, on application of an input pair, that is necessary to characterize robust test-pairs for stuck-open faults. This characterization of robust test-pairs is used to derive:

  1. (i)

    an algorithm for determining if a given test-pair is a robust test-pair for a given stuck-open fault or not; and

  2. (ii)

    a simplified algorithm for computing a robust test-pair for a stuck-open fault. The resulting algorithm for computing robust tests for stuck-open faults can be implemented by minor modifications to test generation algorithms for stuck-at faults.

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Authors and Affiliations

  1. Department of Computer Science, State University of New York, 226 Bell Hall, 14260, Buffalo, NY, USA

    Sreejit Chakravarty

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  1. Sreejit Chakravarty
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Research supported by NSF Grant No. MIP-8807540.

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Chakravarty, S. A characterization of robust test-pairs for stuck-open faults. J Electron Test 1, 275–286 (1991). https://doi.org/10.1007/BF00136316

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  • DOI: https://doi.org/10.1007/BF00136316

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