Abstract
RISC-V is an open Instruction Set Architecture (ISA) released by Berkeley Architecture Group from the University of California, at Berkeley (UCB) in 2010. This paper presents the architecture, design and complete implementation of a 32-bit customisable processor system containing a mix of features as listed below. The 32-bit processor based on RISC-V ISA, is capable of handling atomic operations in addition to all integer operations supported by the ISA. The design has a priority-based nested interrupt controller, giving the user an added flexibility to program the priority levels of interrupts. In addition, there is a debug unit which provides internal visibility during program execution. An error detection and correction interface to memories, makes the design resilient to radiation induced bit-flips. The on-chip communication interface follows the standard Wishbone specification. The design has been implemented on Xilinx Virtex-7 XC7VX48T FPGA and achieves a peak frequency of 80 MHz, with the processor stand-alone operating at 190 MHz. On a 65 nm technology node, the design operates at a frequency of 170 MHz, while the processor stand-alone, a maximum frequency of 220 MHz. The design occupies a footprint of 1.027 mm\(^2\) with 32-KB on-chip memory.
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Sharat, K., Bandishte, S., Varghese, K., Bharadwaj, A. (2017). A Custom Designed RISC-V ISA Compatible Processor for SoC. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_55
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DOI: https://doi.org/10.1007/978-981-10-7470-7_55
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