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SCE: System-on-Chip Environment

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Handbook of Hardware/Software Codesign

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Abstract

The constantly growing complexity of embedded systems is a challenge that drives the development of novel design automation techniques. System-level design can address these complexity challenges by raising the level of abstraction to jointly consider hardware and software as well as by integrating the design processes for heterogeneous system components. In this chapter, we present a comprehensive system-level design framework, the System-on-Chip Environment (SCE) , which is based on the influential SpecC language and methodology. SCE implements a top-down digital system design flow based on a specify-explore-refine paradigm with support for heterogeneous target platforms consisting of custom hardware components, embedded software processors, and complex communication bus architectures. Starting from an abstract specification of the desired system, models at various levels of abstraction are automatically generated through successive stepwise refinement , ultimately resulting in a final pin- and cycle-accurate system implementation. The seamless integration of automatic model generation , estimation , and validation tools enables rapid Design Space Exploration (DSE) and efficient implementation of Multi-Processor Systems-on-Chips (MPSoCs). This article provides an overview and highlights key aspects of the SCE framework from modeling and refinement to hardware and software synthesis. Using a cellphone-based example, our experimental results demonstrate the effectiveness of the SCE framework in terms of system-level exploration, hardware, and software synthesis.

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Abbreviations

API:

Application Programming Interface

AST:

Abstract Syntax Tree

BFM:

Bus-Functional Model

BLM:

Block-Level Model

CE:

Communication Element

DB:

Database

DCT:

Discrete Cosine Transform

DSE:

Design Space Exploration

ESL:

Electronic System Level

FCFS:

First-Come First-Serve

FIFO:

First-In First-Out

FPGA:

Field-Programmable Gate Array

GUI:

Graphical User Interface

HAL:

Hardware Abstraction Layer

HDS:

Hardware-Dependent Software

HLS:

High-Level Synthesis

HW:

Hardware

IDE:

Integrated Development Environment

IP:

Intellectual Property

ISS:

Instruction-Set Simulator

MAC:

Media Access Control

MIPS:

Million Instructions Per Second

MoC:

Model of Computation

MPSoC:

Multi-Processor System-on-Chip

OOO PDES:

Out-of-Order Parallel Discrete Event Simulation

OS:

Operating System

PDES:

Parallel Discrete Event Simulation

PE:

Processing Element

PIC:

Programmable Interrupt Controller

PSM:

Program State Machine

RTL:

Register Transfer Level

RTOS:

Real-Time Operating System

SCE:

System-on-Chip Environment

SLDL:

System-Level Description Language

SW:

Software

TLM:

Transaction-Level Model

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Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Northeastern University, 02115, Boston, MA, USA

    Gunar Schirner

  2. Department of Electrical and Computer Engineering, The University of Texas at Austin, 78712, Austin, TX, USA

    Andreas Gerstlauer

  3. Center for Embedded and Cyber-Physical Systems, Department of Electrical Engineering and Computer Science, The Henry Samueli School of Engineering, University of California, Irvine, 92697-2620, Irvine, CA, USA

    Rainer Dömer

Authors
  1. Gunar Schirner
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  2. Andreas Gerstlauer
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  3. Rainer Dömer
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Corresponding author

Correspondence to Gunar Schirner .

Editor information

Editors and Affiliations

  1. Department of Computer Science and Engineering, Seoul National University, Seoul, Korea (Republic of)

    Soonhoi Ha

  2. Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany

    Jürgen Teich

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Schirner, G., Gerstlauer, A., Dömer, R. (2017). SCE: System-on-Chip Environment. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7267-9_31

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