Concurrent Error Detection Architectures for Field Multiplication Using Gaussian Normal Basis | SpringerLink
Skip to main content
Springer Nature Link
Log in

Concurrent Error Detection Architectures for Field Multiplication Using Gaussian Normal Basis

  • Conference paper
Information Security, Practice and Experience (ISPEC 2010)

Part of the book series: Lecture Notes in Computer Science ((LNSC,volume 6047))

  • 675 Accesses

Abstract

In this investigation, we present a semisystolic type-t(t is even) Gaussian normal basis(GNB) multiplier. Compared with the only existing bit parallel semisystolic even type GNB multiplier, our multiplier saves 10% space complexity and has 50% increase on throughput under the same time complexity. Based on the proposed multiplier, two multipliers with concurrent error detection(CED) capability are developed using two different schemes. The second multiplier with CED capability outperforms previous related works and can be further simply modified to correct certain multiple errors for GNB with type t ≥ 6. Moreover, both the multipliers with CED capability have a high fault coverage. Our results show that any single-cell fault can be detected.

The research is supported by the National High Technology Research and Development Program of China (2009AA01Z417), the National Basic Research Program of China(2007CB807902), Program for New Century Excellent Talents in University(NCET-07-0384) and Foundation for the Author of National Excellent Doctoral Dissertation of China (FANEDD-2007B74).

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution

Subscribe and save

Springer+ Basic
¥17,985 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Chapter
JPY 3498
Price includes VAT (Japan)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
JPY 5719
Price includes VAT (Japan)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
JPY 7149
Price includes VAT (Japan)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. Hankerson, D., Menezes, A., Vanstone, S.: Guide to Elliptic Curve Cryptography. Springer, Heidelberg (2004)

    MATH  Google Scholar 

  2. Nat’l Inst. of Standards and Technology, Digital Signature Standard(DSS), FIPS Publication 186-3 (2009)

    Google Scholar 

  3. IEEE Standard 1363-2000, IEEE Standard Specifications for Public-Key Cryptography (2000)

    Google Scholar 

  4. Boneh, D., DeMillo, R., Lipton, R.: On the Importance of Checking Cryptographic Protocols for Faults. In: Fumy, W. (ed.) EUROCRYPT 1997. LNCS, vol. 1233, pp. 37–51. Springer, Heidelberg (1997)

    Google Scholar 

  5. Kelsey, J., Schneier, B., Wagner, D., Hall, C.: Side-channel Cryptanalysis of Product Ciphers. In: Quisquater, J.-J., Deswarte, Y., Meadows, C., Gollmann, D. (eds.) ESORICS 1998. LNCS, vol. 1485, pp. 97–110. Springer, Heidelberg (1998)

    Chapter  Google Scholar 

  6. Biehl, I., Meyer, B., Müller, V.: Differential Fault Attacks on Elliptic Curve Cryptosystems. In: Bellare, M. (ed.) CRYPTO 2000. LNCS, vol. 1880, pp. 131–146. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

  7. Blömer, J., Otto, M., Seifert, J.P.: Sign Change Fault Attacks on Elliptic Curve Cryptosystems. In: Breveglieri, L., Koren, I., Naccache, D., Seifert, J.-P. (eds.) FDTC 2006. LNCS, vol. 4236, pp. 36–52. Springer, Heidelberg (2006)

    Chapter  Google Scholar 

  8. Massey, J.L., Omura, J.K.: Computational Method and Apparatus for Finite Field Arithmetic, US patent 4,587,627 (1986)

    Google Scholar 

  9. Agnew, G.B., Mullin, R.C., Onyszchuk, I.M., Vanstone, S.A.: An Implementation for a Fast Public-Key Cryptosystem. J. Cryptology 3, 63–79 (1991)

    Article  MATH  MathSciNet  Google Scholar 

  10. Feng, G.-L.: A VLSI Architecture for Fast Inversion in GF(2m). IEEE Trans. Computers 38, 1383–1386 (1989)

    Article  Google Scholar 

  11. Gao, L., Sobelman, G.E.: Improved VLSI Designs for Multiplication and Inversion in GF(2m) over Normal Bases. In: 13th IEEE International ASIC/SOC Conference, pp. 97–101. IEEE Press, New York (2000)

    Google Scholar 

  12. Reyhani-Masoleh, A., Hasan, M.A.: Low Complexity Word-Level Sequential Normal Basis Multipliers. IEEE Trans. Computers 54, 98–110 (2005)

    Article  Google Scholar 

  13. Koç, Ç.K., Sunar, B.: Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields. IEEE Trans. Computers 47, 353–356 (1998)

    Article  Google Scholar 

  14. Reyhani-Masoleh, A., Hasan, M.A.: A New Construction of Massey-Omura Parallel Multiplier over GF(2m). IEEE Trans. Computers 51, 511–520 (2002)

    Article  MathSciNet  Google Scholar 

  15. Kwon, S.: A Low Complexity and a Low Latency Bit Parallel Systolic Multiplier over GF(2m) Using an Optimal Normal Basis of Type II. In: 16th IEEE Symposium on Computer Arithmetic, pp. 196–202. IEEE Press, New York (2003)

    Google Scholar 

  16. Bayat-Sarmadi, S., Hasan, M.A.: Concurrent Error Detection in Finite-Filed Arithmetic Operations Using Pipelined and Systolic Architectures. IEEE Trans. Computers 58, 1553–1567 (2009)

    Article  Google Scholar 

  17. Chiou, C.W., Chang, C.C., Lee, C.Y., Hou, T.W., Lin, J.M.: Concurrent Error Detection and Correction in Gaussian Normal Basis Multiplier over GF(2m). IEEE Trans. Computers 58, 851–857 (2009)

    Article  Google Scholar 

  18. Fenn, S., Gossel, M., Benaissa, M., Taylor, D.: On-Line Error Detection for Bit-Serial Multipliers in GF(2m). J. Electronic Testing: Theory and Applications 13, 29–40 (1998)

    Article  Google Scholar 

  19. Reyhani-Masoleh, A., Hasan, M.A.: Fault Detection Architectures for Field Multiplication Using Polynomial Bases. IEEE Trans. Computers 55, 1089–1103 (2006)

    Article  Google Scholar 

  20. Lee, C.Y., Meher, P.K., Patra, J.C.: Concurrent Error Detection in Bit-Serial Normal Basis Multiplication over GF(2m) Using Multiple Parity Prediction Schemes. IEEE Trans. VLSI (2009) (in Press)

    Google Scholar 

  21. Lee, C.Y.: Concurrent Error Detection in Digital-Serial Normal Basis Multiplication over GF(2m). In: 22nd IEEE International Conference on Advanced Information Networking and Applications, pp. 1499–1504. IEEE Press, New York (2008)

    Google Scholar 

  22. Lee, C.Y.: Concurrent Error Detection Architectures for Gaussian Normal Basis Multiplication over GF(2m). J. VLSI: Integration 43, 113–123 (2010)

    Article  Google Scholar 

  23. Lee, C.Y., Chiou, C.W., Lin, J.M.: Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2m). J. Electronic Testing 22, 143–150 (2006)

    Article  Google Scholar 

  24. Lee, C.Y., Chiou, C.W., Lin, J.M.: Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2m). J. Electronic Testing 21, 539–549 (2005)

    Article  Google Scholar 

  25. Patel, J.H., Fung, L.Y.: Concurrent Error Detection in ALU’s by Recomputing with Shifted Operands. IEEE Trans. Computers 31, 589–595 (1982)

    Article  MATH  Google Scholar 

  26. Patel, J.H., Fung, L.Y.: Concurrent Error Detection in Multiply and Divide Arrays. IEEE Trans. Computers 32, 417–422 (1983)

    Article  MATH  Google Scholar 

  27. Feisel, S., von zur Gathen, J., Shokrollahi, M.A.: Normal Bases via General Gauss Periods. Math. Comput. 68, 271–290 (1999)

    Article  MATH  Google Scholar 

  28. Ash, D.W., Blake, I.F., Vanstone, S.A.: Low Complexity Normal Bases. Discrete Appl. Math. 25, 191–210 (1989)

    Article  MATH  MathSciNet  Google Scholar 

  29. Blake, I.F., Roth, R.M., Seroussi, G.: Efficient Arithmetic in GF(2m) through Palindromic Representation. Technical Report, HPL-98-134 (1998)

    Google Scholar 

  30. McCluskey, E.J.: Design Techniques for Testable Embedded Error Checkers. IEEE Computer 23, 84–88 (1990)

    Google Scholar 

  31. Weste, N., Eshraghian, K.: Principles of CMOS VLSI Design: A system Perspective. Addison-Wesley, Reading (1985)

    Google Scholar 

  32. M74HC08, Quad 2-Input AND Gate, STMicroelectronics (2001), http://www.st.com/stonline/products/literature/ds/1885/m74hc08.pdf

  33. M74HC86,Quad Exclusive OR Gate, STMicroelectronics (2001), http://www.st.com/stonline/products/literature/ds/2006/m74hc86.pdf

  34. M74HC32, Quad 2-Input OR gate, STMicroelectronics (2001), http://www.st.com/stonline/products/literature/ds/1944/m74hc32.pdf

  35. M74HC279, Quad S̄-R̄ Latch, STMicroelectronics (2001), http://www.st.com/stonline/products/literature/od/1937/m74hc279.pdf

Download references

Author information

Authors and Affiliations

  1. Department of Applied Mathematics, Zhengzhou Information Science and Technology Institute, No. 742, P.O. Box 1001, Zhengzhou, 450002, P.R. China

    Zhen Wang, Xiaozhe Wang & Shuqin Fan

Authors
  1. Zhen Wang
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Xiaozhe Wang
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Shuqin Fan
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Department of Information Security Engineering, Soonchunhyang University, 646 Eupnae-ri, Shinchang-myun, Asan-si, 336-745, Chungcheongnam-do, Korea

    Jin Kwak

  2. School of Information Systems, Singapore Management University, 469 Bukit Timah Road, 259756, Singapore

    Robert H. Deng

  3. Internet and Security Policy Division, Korea Internet and Security Agency, Daedong B/D, Garak-dong 79-3, Songpa-gu, 138-950, Seoul, Korea

    Yoojae Won

  4. School of Computer Science, University of Birmingham, B15 2TT, Birmingham, UK

    Guilin Wang

Rights and permissions

Reprints and permissions

Copyright information

© 2010 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Wang, Z., Wang, X., Fan, S. (2010). Concurrent Error Detection Architectures for Field Multiplication Using Gaussian Normal Basis. In: Kwak, J., Deng, R.H., Won, Y., Wang, G. (eds) Information Security, Practice and Experience. ISPEC 2010. Lecture Notes in Computer Science, vol 6047. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12827-1_8

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-12827-1_8

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-12826-4

  • Online ISBN: 978-3-642-12827-1

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation