Abstract
An important design issue of SMT processors is to find proper sharing strategies of resources among threads. This paper proposes a ROB sharing strategy, called paired ROB, that considers the fact that task parallelism is not always available to fully utilize resources of multithreaded processors. To this aim, an evaluation methodology is proposed and used for the experiments, which analyzes performance under different degrees of parallelism. Results show that paired ROBs are a cost-effective strategy that provides better performance than private ROBs for low task parallelism, whereas it incurs slight performance losses for high task parallelism.
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Tullsen, D., Eggers, S., Levy, H.: Simultaneous Multithreading: Maximizing On-Chip Parallelism. In: Proc. of the 22nd Annual International Symposium on Computer Architecture (1995)
El-Moursy, A., Albonesi, D.H.: Front-End Policies for Improved Issue Efficiency in SMT Processors. In: Proc. of the 9th International Conference on High Performance Computer Architecture (February 2003)
Tullsen, D.M., Eggers, S.J., Emer, J.S., Levy, H.M., Lo, J.L., Stamm, R.L.: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. In: Proc. of the 23rd Annual International Symposium on Computer Architecture (May 1996)
Sharkey, J., Balkan, D., Ponomarev, D.: Adaptive Reorder Buffers for SMT Processors. In: Proc. of the 15 International Conference on Parallel Architectures and Compilation Techniques, pp. 244–253 (2006)
Cazorla, F.J., Ramírez, A., Valero, M., Fernández, E.: Dynamically Controlled Resource Allocation in SMT Processors. In: Proc. of the 37th Annual IEEE/ACM International Symposium on Microarchitecture (December 2004)
Choi, S., Yeung, D.: Learning-Based SMT Processor Resource Distribution via Hill-Climbing. In: Proc. of the 33rd Annual International Symposium on Computer Architecture (June 2006)
Raasch, S.E., Reinhardt, S.K.: The Impact of Resource Partitioning on SMT Processors. In: Proc. of the 12th International Conference on Parallel Architectures and Compilation Techniques (October 2003)
Sharkey, J., Ponomarev, D.V.: Efficient Instruction Schedulers for SMT Processors. In: Proc. of the 12th International Symposium on High-Performance Computer Architecture (February 2006)
Yeager, K.C.: The MIPS R10000 Superscalar Microprocessor. IEEE Micro. 16(2), 28–41 (1996)
Ubal, R., Sahuquillo, J., Petit, S., López, P.: Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors. In: Proc. of the 19th International Symposium on Computer Architecture and High Performance Computing (October 2007), http://www.multi2sim.org
Intel Pentium Processor Extreme Edition (4 threads), http://www.intel.com
SPARC Enterprise T5240 (8 threads/core), http://www.fujitsu.com/sparcenterprise
Liu, C., Gaudiot, J.L.: Static Partitioning vs Dynamic Sharing of Resources in Simultaneous Multithreading Microarchitectures. In: Cao, J., Nejdl, W., Xu, M. (eds.) APPT 2005. LNCS, vol. 3756, pp. 81–90. Springer, Heidelberg (2005)
El-Moursy, A., Garg, R., Albonesi, D.H., Dwarkadas, S.: Partitioning Multi-Threaded Processors with a Large Number of Threads. In: Proc. of the IEEE International Symposium on Performance Analysis of Systems and Software (March 2005)
Latorre, F., González, J., González, A.: Back-end Assignment Schemes for Clustered Multithreaded Processors. In: Proc. of the 18th Annual international Conference on Supercomputing (June 2004)
Acosta, C., Falcon, A., Ramírez, A.: A Complexity-Effective Simultaneous Multithreading Architecture. In: Proc. of the 2005 International Conference on Parallel Processing (June 2005)
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Ubal, R., Sahuquillo, J., Petit, S., López, P. (2009). Paired ROBs: A Cost-Effective Reorder Buffer Sharing Strategy for SMT Processors. In: Sips, H., Epema, D., Lin, HX. (eds) Euro-Par 2009 Parallel Processing. Euro-Par 2009. Lecture Notes in Computer Science, vol 5704. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-03869-3_31
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DOI: https://doi.org/10.1007/978-3-642-03869-3_31
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