Abstract
As a critical technology in the embedded system nowadays, program code compression can improve the code density and reduce the power consumption. Especially for the Transport Triggered Architecture (TTA), the long instruction word is one of the key problems to degrade the processor performance. In this paper, with the analysis to the spatial locality of the data transports, a template vertical dictionary-based program compression scheme is proposed. It not only efficiently eliminates the redundant empty slots as well as the invalid long immediate encodings, but also applies the vertical dictionary-based compression at the slot level. The experiment shows that this scheme achieves the compression ratio of 32.3%, especially corresponds to the tiny dictionary size. Then, the effects on area and power consumption are also measured. The total area of the processor core and the local instruction memory could be reduced by about 29% and power consumption by nearly 25% respectively.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Riemens, A.K., Vissers, K.A., Schutten, R.J.: TriMedia CPU64 application domain and benchmark suite. In: ICCD 1999, pp. 580–585 (1999)
TMS320C64x CPU: Instruction Set Reference Guide, Texas Instruments, USA (2000)
Colwell, R.P., Nix, R.P., O’Connel, J.J.: A VLIW architecture for a trace scheduling compiler. IEEE Trans. Comput. 37(8), 679–967 (1988)
Corporaal, H.: Microprocessor Architecture from VLIW to TTA. John Wiley & Sons Ltd, West Sussex, England (1998)
Kuukkanen, P., Takala, J.: Bitwise and dictionary modeling for code compression on transport triggered architectures. WSEAS Transactions on Circuits and Systems 3(9), 1750–1755 (2004)
Heikkinen, J., Rantanen, T., Cilio, A.G.M., Takala, J., Corporaal, H.: Valuating Template-Based Instruction Compression on Transport Triggered Architectures. In: IWSOC 2003, pp. 192–195 (2003)
Heikkinen, J., Cilio, A., Takala, J., Corporaal, H.: Dictionary-Based Program Compression on Transport Triggered Architectures. In: Proc. IEEE Int. Symp. on Circuits and Systems, Kobe, Japan, May 23-26, pp. 1122–1125 (2005)
Hong, Y., Li, S., Kui, D., Zhiying, W.: A TTA-based ASIP design methodology for embedded systems. Journal of Computer Research and Development 43(4), 752–758 (2006)
Witten, I.H., Moffat, A., Bell, T.C.: Managing Gigabytes: Compressing and Indexing Documents and Images. Morgan Kaufmann Publishers, San Francisco, CA, U.S.A. (1999)
Lee, C., Potkonjak, M., Mangione-Smith, W.H.: MediaBench: A tool for evaluating and synthesizing multimedia communications systems. In: Proc. 30th Ann. IEEE/ACM Int. Symp. Microarchitecture, Research Triangle Park, December 1-3, 1997, pp. 330–335 (1997)
Corporaal, H., Hoogerbrugge, J.: Code generation for Transport Triggered Architectures, Code Generation for Embedded Processors (1995)
Heikkinen, J., Takala, J.: Effects of Program Compression. In: Vassiliadis, S., Wong, S., Hämäläinen, T.D. (eds.) SAMOS 2006. LNCS, vol. 4017, pp. 259–268. Springer, Heidelberg (2006)
Data Sheet: PrimePower Full-Chip Dynamic Power Analysis for Multimillion-Gate Design, Synopsys, Inc. (2004)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Mingche, L., Zhiying, W., JianJun, G., Kui, D., Li, S. (2007). Template Vertical Dictionary-Based Program Compression Scheme on the TTA. In: Azémard, N., Svensson, L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74442-9_5
Download citation
DOI: https://doi.org/10.1007/978-3-540-74442-9_5
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-74441-2
Online ISBN: 978-3-540-74442-9
eBook Packages: Computer ScienceComputer Science (R0)