Abstract
This paper aims at comparing multiplication algorithms over \(\mathbb{F}_{{p}^{m}}\)on FPGA. Contrary to previous surveys providing the reader with an estimate of both area and delay in terms of XOR gates, we discuss place-and-route results which point out that the choice of an algorithm depends on the irreducible polynomial and on some architectural parameters. We designed a VHDL code generator to easily study a wide range of algorithms and parameters.
This work was supported by the New Energy and Industrial Technology Development Organization (NEDO), Japan.
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Beuchat, JL., Miyoshi, T., Oyama, Y., Okamoto, E. (2007). Multiplication over \(\mathbb{F}_{{p}^{m}}\) on FPGA: A Survey. In: Diniz, P.C., Marques, E., Bertels, K., Fernandes, M.M., Cardoso, J.M.P. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2007. Lecture Notes in Computer Science, vol 4419. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-71431-6_20
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DOI: https://doi.org/10.1007/978-3-540-71431-6_20
Publisher Name: Springer, Berlin, Heidelberg
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