Abstract
Cache memory represents an important percentage of the total energy consumption of today’s processors. This paper proposes a novel cache design based on data compression to reduce the energy consumed by the data cache. The new scheme stores the same amount of information as a conventional cache but in a smaller physical storage. At the same time, the cache latency is preserved, thus no performance penalty is introduced. The benefits of energy vary from 15.5% to 16%, and the reduction in die area ranges from 23% to 40%.
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Aliagas, C., Molina, C., Garcia, M., Gonzalez, A., Tubella, J. (2003). Value Compression to Reduce Power in Data Caches. In: Kosch, H., Böszörményi, L., Hellwagner, H. (eds) Euro-Par 2003 Parallel Processing. Euro-Par 2003. Lecture Notes in Computer Science, vol 2790. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45209-6_87
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DOI: https://doi.org/10.1007/978-3-540-45209-6_87
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