Abstract
High-performance processors use data-speculation to reduce the execution time of programs. Data-speculation depends on some kind of prediction, and allows the speculative execution of a chain of dependent instructions. On a misprediction, a recovery mechanism must re-issue the speculatively issued instructions. Some recovery mechanisms rely on keeping each instruction in the Issue Queue (IQ) until it is known that the instruction has used correct data. However, their authors either assume that the IQ and the Reorder Buffer (ROB) are unified, or do not detail how the instructions are removed from the IQ before reaching the ROB head entry.
We propose the Verification Issue Queue (VIQ), a mechanism fed with a verification flow graph; the VIQ decides if an instruction can either be removed from the IQ or must be re-issued; the VIQ also allows decoupling the IQ from the ROB. Our evaluations, in the context of load address prediction, show that the verification mechanism is crucial for exploiting the performance potential of data speculation, and that the kind of graph used by the VIQ has a performance impact similar to reducing first-level cache latency by one cycle.
This work was supported by the spanish government (grant CICYT TIC2001-0995-C02-01), and the CEPBA (European Center for Parallelism of Barcelona).
Chapter PDF
Similar content being viewed by others
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
References
Reinman, G., Calder, B.: Predictive techniques for aggressive load speculation. In: International Symposium on Microarchitecture, pp. 127–137 (1998)
Sato, T.: Quantitative evaluation of pipelining and decoupling a dynamic instruction scheduling mechanism. Journal of System Architecture 46(13), 1231–1252 (2000)
Morancho, E., Llabería, J.M., Olivé, À.: Recovery mechanism for latency misprediction. In: Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques, pp. 118–128.
Kessler, R.E.: The alpha 21264 microprocessor. IEEE Micro 19(2), 24–36 (1999)
Diefendorff, K.: Hal makes sparcs fly. Microprocessor Report 13(5) (November 1999)
Sato, T.: Data dependence speculation using data address prediction and its enhancement with instruction reissue. In: 24 th. EUROMICRO Conference Volume 1 (EUROMICRO 1998), August 1998, pp. 285–292. IEEE Computer Society, Los Alamitos (1998)
Sazeides, Y.: An analysis of value predictability and its application to a superscalar processor. Ph.D. Thesis, University of Wisconsin-Madison (1999)
Palacharla, S.: Complexity-effective superscalar processors. Ph.D. Thesis, University of Wisconsin-Madison, Department Computer Science (1998)
Goshima, M., Nishino, K., Kitamura, T., Nakashima, Y., Tomita, S., Ichiro Mori, S.: A high-speed dynamic instruction scheduling scheme for superscalar processors. In: Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, pp. 225–236. IEEE Computer Society, Los Alamitos (2001)
Farrell, J., Fischer, T.C.: Issue logic for a 600-mhz out-of-order execution microprocessor. IEEE Journal of Solid-State Circuits 33(5), 707–712 (1998)
Burger, D., Austin, T., Bennet, S.: Evaluating future microprocessors: The simplescalar tool set. University of Wisconsin-Madison, Department Computer Science, Tech. Rep. CS-TR-96-1308 (1996)
Morancho, E.: Address prediction and recovery mechanisms. Ph.D. Thesis, Dept. of Computer Architecture, Universidad Politècnica de Catalunya (May 2002)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Morancho, E., Llabería, J.M., Olivé, À. (2004). A Mechanism for Verifying Data Speculation. In: Danelutto, M., Vanneschi, M., Laforenza, D. (eds) Euro-Par 2004 Parallel Processing. Euro-Par 2004. Lecture Notes in Computer Science, vol 3149. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-27866-5_69
Download citation
DOI: https://doi.org/10.1007/978-3-540-27866-5_69
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22924-7
Online ISBN: 978-3-540-27866-5
eBook Packages: Springer Book Archive