Abstract
Simulation platforms for network processing still have difficulties in finding a good compromise between speed and accuracy. This makes it difficult to identify the causes of performance bottlenecks: Are they caused by application, hardware architecture, or by a specificity of the operating system? We propose a simulation methodology for a multiprocessor network processing platform which contains sufficient detail to permit very precise simulation and performance evaluation while staying within reasonable limits of both specification and simulation time. As a case study, we show how a model can be developed for a IPv4 packet routing application, exhibiting the performance and scalability bottlenecks and can thus be used to reason about architectural alternatives.
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References
Shah, N.: Understanding network processors. Master’s thesis, Dept. of Electrical Eng. and Computer Science, Univ. of California, Berkeley (2001)
Paulin, P., Pilkington, C., Bensoudane, E.: STepNP Platform. Ottawa, Canada (2002)
Cai, L., Gajski, D.: Transaction level modelling in system level design. Tr, Univ. of California, Irvine (2003)
Open SystemC Initiative: SystemC. Technical report, OSCI (2003), http://www.systemc.org
Groetker, T., Liao, S., Martin, G., Swain, S.: System Design in SystemC. Kluwer, Dordrecht (2002)
SOCLIB Consortium: Projet SOCLIB: Plate-forme de modélisation et de simulation de systèmes integrés sur puce (the SOCLIB project: An integrated system-onchip modelling and simulation platform). Technical report, CNRS (2003), http://soclib.lip6.fr
VSI Alliance: Virtual Component Interface Standard (OCB 2 2.0). Technical report, VSI Alliance (2000), http://www.vsi.org/library/specs/summary.htm#ocb
Baker, F.: Requirements for ip version 4 router. Internet Eng. Task Force (1995), ftp://ftp.ietf.org/rfc/rfc1812.txt
Kohler, E.: Click system free software (1995), http://www.pdos.lcs.mit.edu/click
Kohler, E.: The Click modular router. PhD thesis, Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science (2000)
Andriahantenaina, A., Charléry, H., Greiner, A., Mortiez, L., Zeferino, C.: SPIN: a scalable, packet switched, on-chip micro-network. In: Design Automation and Test in Europe Conference (DATE 2003) Embedded Software Forum, Muenchen, Germany, pp. 70–73 (2003)
Chen, B., Morris, R.: Flexible control of parallelism in a multiprocessor PC router. In: Proceedings of the, USENIX Annual Technical Conference (USENIX-01), Berkeley, CA, The USENIX Association, pp. 333–346 (2001)
Pétrot, F., Gomez, P., Hommais, D.: Lightweight implementation of the POSIX threads API for an on-chip mips multiprocessor with VCI interconnect. In: Jerraya, A.A., Yoo, S., Verkest, D., Wehn, N. (eds.) Embedded Software for SoC, pp. 25–38. Kluwer Academic Publishers, Dordrecht (2003)
Tanenbaum, A.: Distributed Operating Systems, pp. 169–185. Prentice-Hall, Englewood Cliffs (1995)
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© 2004 Springer-Verlag Berlin Heidelberg
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Berrayana, S., Faure, E., Genius, D., Pétrot, F. (2004). Modular On-chip Multiprocessor for Routing Applications. In: Danelutto, M., Vanneschi, M., Laforenza, D. (eds) Euro-Par 2004 Parallel Processing. Euro-Par 2004. Lecture Notes in Computer Science, vol 3149. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-27866-5_113
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DOI: https://doi.org/10.1007/978-3-540-27866-5_113
Publisher Name: Springer, Berlin, Heidelberg
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