Abstract
Using multi-core architectures for embedded time-critical systems creates a big challenge for developers due to the complexity of the underline mapping and scheduling problem. H2020 ARGO project [2] proposes a tool flow to minimize multi-core applications development time while guaranteeing real-time performance. In this paper, we provide an overview of ARGO tool flow and we focus on the heuristic approach of solving the worst case execution time aware (WCET) mapping and scheduling problem on hierarchical task graphs. Examples from two real applications from the aerospace and image processing domains are presented.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Bittencourt, L.F., Sakellariou, R., Madeira, E.R.M.: DAG scheduling using a lookahead variant of the heterogeneous earliest finish time algorithm. In: 2010 18th Euromicro Conference on Parallel, Distributed Network-Based Processing, pp. 27–34 (2010)
Derrien, S., Puaut, I., Alefragis, P., Bednara, M., Bucher, H., David, C., Debray, Y., Durak, U., Fassi, I., Ferdinand, C., Hardy, D., Kritikakou, A., Rauwerda, G., Reder, S., Sicks, M., Stripf, T., Sunesen, K., ter Braak, T., Voros, N., Becker, J.: WCET-aware parallelization of model-based applications for multi-cores: the ARGO approach. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), Lausanne, Switzerland, pp. 286–289. IEEE (2017)
Emeretlis, A., Theodoridis, G., Alefragis, P., Voros, N.: A logic-based benders decomposition approach for mapping applications on heterogeneous multicore platforms. ACM Trans. Embed. Comput. Syst. 15, 1–28 (2016). ACM
Emeretlis, A., Theodoridis, G., Alefragis, P., Voros, N.: A hybrid approach for mapping and scheduling on heterogeneous multicore systems. In: 2016 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Samos, Greece (2016)
Floch, A., Yuki, T., Moussawi, A.E., Morvan, A., Martin, K., Naullet, M., Alle, M., L’Hours, L., Simon, N., Derrien, S., Charot, F., Wolinski, C., Sentieys, O.: GeCoS: a framework for prototyping custom hardware design flows. In: Proceedings of the 13th IEEE International Working Conference on Source Code Analysis and Manipulation, SCAM 2013, Eindhoven, Netherlands, 22–23 September 2013, pp. 100–105. IEEE (2013)
Jovanovic, O., Kneuper, N., Engel, M., Marwedel, P.: ILP-based memory-aware mapping optimization for MPSoCs. In: 2012 IEEE 15th International Conference on Computational Science and Engineering, pp. 413–420. IEEE (2012)
Kelter, T., Borghorst, H., Marwedel, P.: WCET-aware scheduling optimizations for multi-core real-time systems. In: XIVth International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2014, Agios Konstantinos, Samos, Greece, 14–17 July 2014, pp. 67–74 (2014)
Kwok, Y.-K., Ahmad, I.: Dynamic critical-path scheduling: an effective technique for allocating task graphs to multiprocessors. IEEE Trans. Parallel Distrib. Syst. 7(5), 506–521 (1996). IEEE
Stripf, T., Oey, O., Bruckschloegl, T., et al.: A compilation - and simulation - oriented architecture description language for multicore systems. In: IEEE Proceedings of 15th IEEE International Conference on Computational Science and Engineering (CSE), pp. 383–390. IEEE (2012). https://doi.org/10.1109/iccse.2012.60. ISBN 978-1-4673-5165-2
Stripf, T., Oey, O., Bruckschloegl, T., Becker, J., Rauwerda, G., Sunesen, K., Goulas, G., Alefragis, P., Voros, N.S., Derrien, S., Sentieys, O., Kavvadias, N., Dimitroulakos, G., Masselos, K., Kritharidis, D., Mitas, N., Perschke, T.: Compiling Scilab to high performance embedded multicore systems. Microprocess. Microsyst. 37, 1033–1049 (2013). Elsevier
Topcuoglu, H., Hariri, S., Wu, M.-Y.: Task scheduling algorithms for heterogeneous processors. In: Proceedings of the 8th Heterogeneous Computing Workshop. IEEE (1999). https://doi.org/10.1109/hcw.1999.765092
Wilhelm, R., Engblom, J., Ermedahl, A., Holsti, N., Thesing, S., Whalley, D., Bernat, G., Ferdinand, C., Heckmann, R., Mitra, T., Mueller, F., Puaut, I., Puschner, P., Staschulat, J., Stenstrom, P.: The worst-case execution-time problem – overview of methods and survey of tools. ACM Trans. Embed. Comput. Syst. 7, 36:1–36:53 (2008)
Acknowledgement
This work was funded by the European Union under the Horizon 2020 Framework Program under grant agreement ICT-2015-688131, project “WCET-Aware Parallelization of Model-Based Applications for Heterogeneous Parallel Systems (ARGO)”.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer International Publishing AG, part of Springer Nature
About this paper
Cite this paper
Alefragis, P. et al. (2018). Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2018. Lecture Notes in Computer Science(), vol 10824. Springer, Cham. https://doi.org/10.1007/978-3-319-78890-6_56
Download citation
DOI: https://doi.org/10.1007/978-3-319-78890-6_56
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-78889-0
Online ISBN: 978-3-319-78890-6
eBook Packages: Computer ScienceComputer Science (R0)