Abstract
This paper presents the work that will be done in the research project “DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications”. The project focuses on transferring knowledge on partial and dynamic reconfiguration of FPGAs from the academic partners to small and medium enterprises (SMEs), because the success stories on partial and dynamic reconfiguration were mainly only realized in large companies with a substantial amount of R&D activities. The reason is that the technology is still perceived as being difficult to adopt and expensive in terms of NRE costs. Therefore, the goal of the DynamIA project is two-fold. (1) It develops a number of use cases and guidelines in different application domains, tailored to the activities of the SMEs in the user group and in the broader target group. These use cases demonstrate a number of benefits of partial and dynamic FPGA reconfiguration, namely a faster startup, a faster design cycle and a lower occupation of resources leading to a lower static power consumption. (2) It develops a low-cost, vendor-independent emulation environment for dynamic and partial reconfiguration, which is non-existing in commercial and academic EDA tools. Another benefit of this emulation environment is that it can also be used for static designs. This allows SMEs to have a low-cost emulation environment for their applications instead of developing their own emulation environment manually (which is very time-consuming) or buying big cost-intensive commercial emulators.
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References
Altera. Increasing design functionality with partial and dynamic reconfiguration in 28-nm FPGAs. White Paper, Altera Corporation (2010)
FPGA developer: Tools and tutorials for FPGA designers. List and comparison of FPGA companies (2011). http://www.fpgadeveloper.com/2011/07/list-and-comparison-of-fpga-companies.html
De Hon, A.: Reconfigurable architectures for general-purpose computing. AI Technical Report 1586, MIT Artificial Intelligence Laboratory (1996)
Huebner, M., Meyer, J., Sander, O., Braun, L., Becker, J., Noguera, J., Stewart, R.: Fast sequential FPGA startup based on partial and dynamic reconfiguration. In: Proc. of the IEEE Computer Society Annual Symp. on VLSI (ISVLSI) (2010)
Al Kadi, M.S., Ferger, M., Stegemann, V., Huebner, M.: Multi-FPGA reconfigurable system for accelerating MATLAB simulations. In: Proc. of the Intl. Conf. on Field Programmable Logic (FPL). IEEE (2014)
Schwiegelshohn, F., Huebner, M.: An application scenario for dynamically reconfigurable FPGAs. In: Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC). IEEE (2014)
Trimberger, S., Carberry, D., Johnson, A., Wong, J.: A time-multiplexed FPGA. In: Proc. of the 5th Annual IEEE Symp. on FPGAs for Custom Computing Machines, vol. 4833, pp. 22–28 (1997)
Xilinx. Xcell journal (1988–2012). http://www.xilinx.com/publications/xcellonline
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© 2015 Springer International Publishing Switzerland
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Mentens, N. et al. (2015). DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications. In: Sano, K., Soudris, D., Hübner, M., Diniz, P. (eds) Applied Reconfigurable Computing. ARC 2015. Lecture Notes in Computer Science(), vol 9040. Springer, Cham. https://doi.org/10.1007/978-3-319-16214-0_47
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DOI: https://doi.org/10.1007/978-3-319-16214-0_47
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