Abstract
While fine-grain, reconfigurable devices have been available for years, they are mostly used in a fixed functionality, “asic-replacement” manner. To exploit opportunities for flexible and adaptable run-time exploitation of fine grain reconfigurable resources (as implemented currently in dynamic, partial reconfiguration), better tool support is needed. The FASTER project aims to provide a methodology and a tool-chain that will enable designers to efficiently implement a reconfigurable system on a platform combining software and reconfigurable resources. Starting from a high-level application description and a target platform, our tools analyse the application, evaluate reconfiguration options, and implement the designer choices on underlying vendor tools. In addition, FASTER addresses micro-reconfiguration, verification, and the run-time management of system resources. We use industrial applications to demonstrate the effectiveness of the proposed framework and identify new opportunities for reconfigurable technologies.
The FASTER project is supported by the European Commission Seventh Framework Programme, grant agreement #287804. http://www.fp7-faster.eu/
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References
Sourdis, I., Pnevmatikatos, D., Vassiliadis, S.: Scalable Multi-Gigabit Pattern Matching for Packet Inspection. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16(2), 156–166 (2008)
Bruneel, K., Stroobandt, D.: Automatic Generation of Run-Time Parameterizable Configurations. In: IEEE International Conference on Field Programmable Logic and Applications (FPL), pp. 361–366 (August 2008)
Cattaneo, R., Pilato, C., Mastinu, M., Kadlcek, O., Pell, O., Santambrogio, M.D.: Runtime Adaptation on Dataflow HPC Platforms. In: NASA/ESA Conference on Adaptive Hardware and Systems (AHS) (June 2013)
Todman, T., Luk, W.: Verification of Streaming Designs by Combining Symbolic Simulation and Equivalence Checking. In: IEEE International Conference on Field Programmable Logic and Applications (FPL) (August 2012)
http://www.hartes.org/ (accessed 2012)
http://www.reflect-project.eu/ (accessed 2012)
http://www.hitech-projects.com/euprojects/ACOTES/ (accessed 2014)
http://andres.offis.de/ (accessed 2014)
http://www.era-project.eu/ (accessed 2014)
Pnevmatikatos, D., Becker, T., Brokalakis, A., Bruneel, K., Gaydadjiev, G., Luk, W., Papadimitriou, K., Papaefstathiou, I., Pell, O., Pilato, C., Robart, M., Santambrogio, M.D., Sciuto, D., Stroobandt, D., Todman, T.: FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration. In: Euromicro Conference on Digital System Design (DSD) (September 2012)
Durelli, G., Pilato, C., Cazzaniga, A., Sciuto, D., Santambrogio, M.D.: Automatic Run-Time Manager Generation for Reconfigurable MPSoC Architectures. In: IEEE International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) (July 2012)
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Pnevmatikatos, D.N. et al. (2014). Effective Reconfigurable Design: The FASTER Approach. In: Goehringer, D., Santambrogio, M.D., Cardoso, J.M.P., Bertels, K. (eds) Reconfigurable Computing: Architectures, Tools, and Applications. ARC 2014. Lecture Notes in Computer Science, vol 8405. Springer, Cham. https://doi.org/10.1007/978-3-319-05960-0_35
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DOI: https://doi.org/10.1007/978-3-319-05960-0_35
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