Abstract
Recently, image/video-based applications have been widely used for many domains, such as traffic, medical, or robotics. In this context, IoT-based systems with video processing implemented on edge devices have been applied extensively, for example, surveillance, object detection and monitoring, or intelligent home/building systems. Although algorithms for images/videos encoder with various standards produce good results, they usually require high computing power that is limited with edge platforms. Therefore, we propose an efficient hardware/software codesign approach to accelerate the video encoder process with FPGA-based IoT edge computing platforms in this work. The design flow exploits the effectiveness of the high-level synthesis process to quickly and efficiently generate FPGA-based hardware accelerator cores to improve system performance. We use the H.264 encoder as our case study to verify the proposed design flow and evaluate the accelerator ability compared to general-purpose processors. An FPGA Ultra96-v2 edge computing board is used for conducting experiments with a certified dataset. Experimental results show that we obtain speed-ups by up to 14.9\(\times \) compared to a 4-core ARM processor. Our experimental system also saves up to 6.24\(\times \) energy consumption compared to the ARM processor.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
AMD Xilinx. Vitis\(^{\rm TM}\) unified software platform overview (2023). https://www.xilinx.com/products/design-tools/vitis/vitis-platform.html. Accessed 01 Apr 2023
Cadence. Stratus high-level synthesis fastest path from specification to silicon (2023). https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/digital-design-signoff/stratus-high-level-synthesis-ds.pdf. Accessed 01 Apr 2023
Caprolu, M., Di Pietro, R., Lombardi, F., Raponi, S.: Edge computing perspectives: Architectures, technologies, and open security issues. In: 2019 IEEE International Conference on Edge Computing (EDGE), pp. 116–123 (2019). https://doi.org/10.1109/EDGE.2019.00035
Garrido, M.J., Pescador, F., Chavarrías, M., Lobo, P.J., Sanz, C., Paz, P.: An FPGA-based architecture for the versatile video coding multiple transform selection core. IEEE Access 8, 81887–81903 (2020). https://doi.org/10.1109/ACCESS.2020.2991299
Gupta, R., Brewer, F.: High-Level Synthesis: A Retrospective, pp. 13–28. Springer, Netherlands (2008). https://doi.org/10.1007/978-1-4020-8588-8_2
International Telecommunication Union. H.264.2: Reference software for itu-t h.264 advanced video coding (2016). https://www.itu.int/rec/T-REC-H.264.2. Accessed 01 Apr 2023
Joint Video Team. H.264/14496-10 AVC reference software manual (2009). https://iphome.hhi.de/. Accessed 01 Apr 2023
Martin, G., Smith, G.: High-level synthesis: Past, present, and future. IEEE Design Test Comput. 26(4), 18–25 (2009). https://doi.org/10.1109/MDT.2009.83
Mukherjee, A.: VLSI architecture design of motion estimation block with hexagon-diamond search pattern for real-time video processing. In: 2021 IEEE 18th India Council International Conference (INDICON), pp. 1–6 (2021). https://doi.org/10.1109/INDICON52576.2021.9691531
Pastuszak, G.: Multisymbol architecture of the entropy coder for h.265/hevc video encoders. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems vol. 28, no. 12, pp. 2573–2583 (2020). https://doi.org/10.1109/TVLSI.2020.3016386
Pham-Quoc, C., Al-Ars, Z., Bertels, K.: A heuristic-based communication-aware hardware optimization approach in heterogeneous multicore systems. In: 2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012 (2012). https://doi.org/10.1109/ReConFig.2012.6416720
Pham-Quoc, C., Heisswolf, J., Werner, S., Al-Ars, Z., Becker, J., Bertels, K.: Hybrid interconnect design for heterogeneous hardware accelerators. In: 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 843–846 (2013). https://doi.org/10.7873/DATE.2013.178
Qiu, Y., et al.: A heterogeneous HEVC video encoder system based on two-level CPU-FPGA computing architecture. In: 2021 IEEE 14th International Conference on ASIC (ASICON), pp. 1–4 (2021). https://doi.org/10.1109/ASICON52560.2021.9620382
Richardson, I.E.: The H.264 Advanced Video Compression Standard, 2nd edn. Wiley Publishing (2010)
Roman, R., Lopez, J., Mambo, M.: Mobile edge computing, fog et al.: A survey and analysis of security threats and challenges. Future Gen. Comput. Syst. 78, 680–698 (2018). https://doi.org/10.1016/j.future.2016.11.009
Sjövall, P., Rasinen, M., Lemmetti, A., Vanne, J.: High-level synthesis implementation of an accurate hevc interpolation filter on an FPGA. In: 2021 IEEE Nordic Circuits and Systems Conference (NorCAS), pp. 1–7 (2021). https://doi.org/10.1109/NorCAS53631.2021.9599653
Tao, L., Gao, W.: A hardware implementation of entropy encoder for 8k video coding. In: 2022 IEEE International Conference on Multimedia and Expo (ICME), pp. 1–6 (2022). https://doi.org/10.1109/ICME52920.2022.9859988
The Linux Kernel Archives: perf: Linux profiling with performance counters (2023). https://perf.wiki.kernel.org/. Accessed 01 Apr 2023
VideoLAN Organization: x264, the best h.264/avc encoder (2013). http://www.videolan.org/developers/x264.html. Accessed 01 Apr 2023
Waidyasooriya, H.M., et al.: Opencl-based design of an FPGA accelerator for h.266/vvc transform and quantization. In: 2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1–4 (2022). https://doi.org/10.1109/MWSCAS54063.2022.9859281
Xilinx. Zynq ultrascale+ mpsoc (2021). https://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html. Accessed 01 Apr 2023
Xilinx, A.: Vitis high-level synthesis user guide (ug1399) (2022). https://docs.xilinx.com/r/en-US/ug1399-vitis-hls. Accessed 01 Apr 2023
Xiph.org. Video test media [derf’s collection] (2016). https://media.xiph.org/video/derf/. Accessed 01 Apr 2023
Acknowledgement
We acknowledge Ho Chi Minh City University of Technology (HCMUT), VNU- HCM for supporting this study.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2023 The Author(s), under exclusive license to Springer Nature Switzerland AG
About this paper
Cite this paper
Pham-Quoc, C. (2023). FPGA-Based Hardware/Software Codesign for Video Encoder on IoT Edge Platforms. In: Gervasi, O., et al. Computational Science and Its Applications – ICCSA 2023 Workshops. ICCSA 2023. Lecture Notes in Computer Science, vol 14108. Springer, Cham. https://doi.org/10.1007/978-3-031-37117-2_7
Download citation
DOI: https://doi.org/10.1007/978-3-031-37117-2_7
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-031-37116-5
Online ISBN: 978-3-031-37117-2
eBook Packages: Computer ScienceComputer Science (R0)