Abstract
With the growing complexity of embedded applications, system architects integrate more processors into System-on-Chip (SoC) designs. Since scalability of such systems is a key criterion for their efficiency, regular array-type architectures are preferred that can easily grow in size. In this work, we model in SystemC TLM-2.0 a Grid of Processing Cells (GPC) with a Checkerboard arrangement of processors and memories. To demonstrate its scalability, we evaluate the performance of a highly parallel Mandelbrot renderer on growing Checkerboard platforms. Our results confirm that the performance scales well with the number of processors.
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Notes
- 1.
Please note that the irrelevant timing delays do not include contention time when modules wait for access to shared bus resources. Contention is a very relevant criterion when comparing system architectures with shared resources and would be highly desirable in our comparison. However, measurement of contention was unfortunately not yet available in the described models at the time of the experiments reported in this section.
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Wang, Y., Daroui, A., Dömer, R. (2023). Demonstrating Scalability of the Checkerboard GPC with SystemC TLM-2.0. In: Henkler, S., Kreutz, M., Wehrmeister, M.A., Götz, M., Rettberg, A. (eds) Designing Modern Embedded Systems: Software, Hardware, and Applications. IESS 2022. IFIP Advances in Information and Communication Technology, vol 669. Springer, Cham. https://doi.org/10.1007/978-3-031-34214-1_6
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