Abstract
The use of OpenSHMEM has traditionally focused on supporting a one-sided communication mechanism between networked processors. The US Army Research Laboratory (ARL) OpenSHMEM implementation for the Epiphany architecture has highlighted the utility of OpenSHMEM for the precise control of on-die data movement within arrays of RISC cores connected by a 2D mesh Network on Chip (NoC), and was demonstrated using a 16-core Epiphany-III coprocessor. More recently, DARPA has fabricated a much larger 64-bit 1,024-core Epiphany-V device, which ARL is presently evaluating. In support of this effort, we have developed an Epiphany-based RISC SoC device emulator that can be installed as a virtual device on an ordinary x86 platform and utilized with the existing software stack used to support physical devices, thus creating a seamless software development environment capable of targeting new processor designs just as they would be interfaced on a real platform. As massively parallel processor arrays (MPPAs) emerge as a strong contender for future exascale architectures, we investigate the application of OpenSHMEM as a programming model for processors with hundreds to thousands of cores. In this work we report on the initial results from scaling up the ARL OpenSHMEM implementation using virtual RISC processors with much larger core counts than previous physical devices.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
https://www.top500.org/lists/2017/11/. Accessed 18 June 2018
https://www.top500.org/green500/lists/2017/11/. Accessed 18 June 2018
https://www.nitrd.gov/nitrdgroups/images/b/b4/NSA_DOE_HPC_TechMeetingReport.pdf. Accessed 04 Feb 2018
Adapteva introduction. http://www.adapteva.com/introduction/. Accessed 08 Jan 2015
Olofsson, A., Nordström, T., Ul-Abdin, Z.: Kickstarting high-performance energy-efficient manycore architectures with Epiphany. ArXiv Prepr. ArXiv:14125538 (2014)
Wentzlaff, D., et al.: On-chip interconnection architecture of the tile processor. IEEE Micro 27(5), 15–31 (2007)
Taylor, M.B., et al.: A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network. In: 2003 IEEE International Solid-State Circuits Conference (ISSCC), pp. 170–171 (2003)
Epiphany-V: A 1024-core processor 64-bit System-On-Chip. http://www.parallella.org/docs/e5_1024core_soc.pdf. Accessed 10 Feb 2017
Ross, J., Richie, D.: An OpenSHMEM implementation for the Adapteva epiphany coprocessor. In: OpenSHMEM and Related Technologies. Enhancing OpenSHMEM for Hybrid Environments, vol. 10007, pp. 146–159, December 2016. https://doi.org/10.1007/978-3-319-50995-2_10
Richie, D., Ross, J.: Architecture emulation and simulation of future many-core epiphany RISC array processors. In: International Conference on Computational Science, ICCS 2018, Wuxi, China, 11–13 June 2018
Richie, D., Ross, J.: Advances in run-time performance and interoperability for the Adapteva epiphany coprocessor. Procedia Comput. Sci. 80 (2016). https://doi.org/10.1016/j.procs.2016.05.47
Acknowledgements
This work was supported by the U.S. Army Research Laboratory. Without the relative openness of the Adapteva Epiphany architecture and ISA, this work would have been more difficult.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Switzerland AG
About this paper
Cite this paper
Ross, J.A., Richie, D.A. (2019). Scaling OpenSHMEM for Massively Parallel Processor Arrays. In: Pophale, S., Imam, N., Aderholdt, F., Gorentla Venkata, M. (eds) OpenSHMEM and Related Technologies. OpenSHMEM in the Era of Extreme Heterogeneity. OpenSHMEM 2018. Lecture Notes in Computer Science(), vol 11283. Springer, Cham. https://doi.org/10.1007/978-3-030-04918-8_9
Download citation
DOI: https://doi.org/10.1007/978-3-030-04918-8_9
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-04917-1
Online ISBN: 978-3-030-04918-8
eBook Packages: Computer ScienceComputer Science (R0)